A practical tool box for system level communication synthesis

Hommais, D.; Pétrot, Frédéric; Augé, Ivan

doi:10.1109/hsc.2001.924649

Cited by 6 publications

(2 citation statements)

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“…We chose an abstraction level which is the input for high-level hardware synthesis [17] and its industrial applications [11]. The system to analyse is modelled by a finite set of concurrent asynchronous processes.…”

Section: Contextmentioning

confidence: 99%

Data decision diagrams for Promela systems analysis

Beaudenon

Encrenaz

Taktak

2010

Int J Softw Tools Technol Transfer

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In this paper, we show how to verify CTL properties, using symbolic methods, on systems written in ProMeLa. Symbolic representation is based on Data Decision Diagrams (DDDs) which are n-valued DAGs designed to represent dynamic systems with integer domain variables. We describe principal components used for the verification of ProMeLa systems (DDD, representation of ProMeLa programs with DDD, the transposition of the execution of ProMeLa instructions into DDD). Then we compare and contrast our method with the model checker SPIN or classical BDD techniques, to highlight what system classes whether SPIN or our tool is more relevant for.

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Section: Contextmentioning

confidence: 99%

Data decision diagrams for Promela systems analysis

Beaudenon

Encrenaz

Taktak

2010

Int J Softw Tools Technol Transfer

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“…row-column), Input/Output parallelism adaptation. Based on communication templates, [9] presents a generic interface unit architecture for communication synthesis in a platform-based design approach. In [1] a multiplexer/demultiplexer and FIFO-based interface architecture is used.…”

Section: Introductionmentioning

confidence: 99%

A design methodology for space-time adapter

Coussy¹,

Urard

Martin

2007

Proceedings of the 17th ACM Great Lakes Symposium on VLSI

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This paper presents a solution to efficiently explore the design space of communication adapters. In most digital signal processing (DSP) applications, the overall architecture of the system is significantly affected by communication architecture, so the designers need specifically optimized adapters. By explicitly modeling these communications within an effective graphtheoretic model and analysis framework, we automatically generate an optimized architecture, named Space-Time AdapteR (STAR). Our design flow inputs a C description of Input/Output data scheduling, and user requirements (throughput, latency, parallelism…), and formalizes communication constraints through a Resource Constraints Graph (RCG). The RCG properties enable an efficient architecture space exploration in order to synthesize a STAR component. The proposed approach has been tested to design an industrial data mixing block example: an Ultra-Wideband interleaver.

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