A practical methodology for early buffer and wire resource allocation

Abstract

Abstract-As technology scales, interconnect-centric design flows become imperative for achieving timing closure. Preplanning buffers and wires in the layout is critical for such flows. Both buffers and wires must be considered simultaneously, since wire routes determine buffer requirements and buffer locations constrain the wire routes. In contrast to recently proposed buffer-block planning approaches, our novel design methodology distributes a set of buffer sites throughout the design. This allows one to use a tile graph to abstract the buffer planning problem and simultaneously address wire planning. We present a four-stage heuristic called resource allocation for buffer and interconnect distribution for resource allocation that includes a new, efficient technique for buffer insertion using a length-based constraint. Extensive experiments validate the effectiveness of this approach.

Improved predictability, timing yield and power consumption using hierarchical highways-on-chip planning methodology

“…This may reduce the number of planned nets and degrade the accuracy of estimations and planning [13]. Finally, the last drawback of the proposed methods is that they may cause some congested areas to be created in the channels between the macros [12] due to inserting many buffers in the spaces between the macros.…”

“…However, estimation of final parameters in higher levels of physical design (such as floorplanning) is very rough and should not be used to fix the final values of design parameters. In other words, fixing the detail features of interconnects at early stages based on high-level estimations can be very erroneous [12]. The second limitation of the above methodologies is that they only plan those interconnects that connect floorplanning macros together and all internal wires of the macros are neglected.…”

“…Alpert et al [12] proposed a methodology for early buffer planning considering the wires inside the macros. They reserved some internal areas of the macros (buffer sites) for early buffer planning.…”

Chip master planning: An efficient methodology to improve design closure and complexity management of ultra large chips

“…However, estimation of final parameters in higher levels of physical design (such as floorplanning) is very rough and should not be used to fix the final values of design parameters. Therefore, fixing the detail features of interconnects at early stages based on high-level estimations can be very erroneous [8]. The second limitation of the above methodologies is that they only plan those interconnects that connect floorplanning macros together and all internal wires of the macros are neglected.…”

Handling routability in floorplan design with twin binary trees

“…Dragan et al [6] used a multi-commodity flow-based approach to allocate buffers to some pre-existing buffer blocks such that the required upper and lower bound on intervals between buffers can be satisfied as much as possible. Alpert et al [1] made use of tile graph and dynamic programming to perform buffer block planning. The papers [9,13]considered congestion and buffer positions simultaneously.…”