A Practical, Hardware Friendly MMSE Detector for MIMO-OFDM-Based Systems

Abstract

Design and implementation of a highly optimized MIMO (multiple-input multiple-output) detector requires cooptimization of the algorithm with the underlying hardware architecture. Special attention must be paid to application requirements such as throughput, latency, and resource constraints. In this work, we focus on a highly optimized matrix inversion free 4 × 4 MMSE (minimum mean square error) MIMO detector implementation. The work has resulted in a real-time field-programmable gate array-based implementation (FPGA-) on a Xilinx Virtex-2 6000 using only 9003 logic slices, 66 multipliers, and 24 Block RAMs (less than 33% of the overall resources of this part). The design delivers over 420 Mbps sustained throughput with a small 2.77microsecond latency. The designed 4 × 4 linear MMSE MIMO detector is capable of complying with the proposed IEEE 802.11n standard.

ASIP Design and Prototyping for Wireless Communication Applications

“…Using analytic method of matrix inversion, a fully dedicated architecture for MMSE-IC1 LE for 2×2 turbo MIMO system with pre-coding used in quasi static channel has been proposed in . The other work carried out in (Kim et al, 2008) shows exciting results in terms of throughput for 802.11n MIMO-OFDM application. The implementation is based on a inverse free architecture using square-root MMSE formulation.…”

“…All of the referenced implementations present dedicated architecture for a specific system configuration except (Eilert et al, 2007) where the proposed architecture supports 2×2 and 4×4 matrix inversion. Table 4 is organized in such a way that first of all comparison is made with (Boher et al, 2008), (Kim et al, 2008) and ) which provide a complete solution to generate estimated symbol vectors. Then comparison with (Myllyla et al, 2005) (providing solution to compute only the coefficient matrix of Equation 3) is tabulated.…”

“…Hence, the flexibility of EquASIP to support 5 different STC comes at the cost of 2.4 times less throughput, 53% more slice registers and 16 more dedicated multipliers compared to (Boher et al, 2008). In (Kim et al, 2008), the architecture implements 4×4 MIMO SM detector for 802.11n standard. In this application the design is made for a worst case scenario where for 48 vectors channel remains constant.…”

“…In this application the design is made for a worst case scenario where for 48 vectors channel remains constant. To decode a frame of 48 vectors, the work in (Kim et al, 2008) Table 4. EquASIP performance comparison comparing with our work, this EquASIP consumes 221 clock cycles to compute equalization coefficient for a frame and 13 clock cycles for each vector estimation.…”

“…Hence the total consumed clock cycles for 48 vectors estimation are 221 + 13×48 = 845 which results in a throughput of 4.7 M vectors per second at a frequency of 83 MHz. Hence, throughput of the dedicated architecture of (Kim et al, 2008) is almost 3.6 times more at a cost of almost twice the FPGA slice used and 7.5 times more multipliers. Again this implementation is not flexible for variable antenna size, time selectivity of the channel and iterative nature of equalization.…”