A power and resolution adaptive flash analog-to-digital converter

Yoo, Jincheol; Lee, Daegyu; Choi, Kwing-So; Kim, Jong-Soo

doi:10.1145/566465.566468

Cited by 5 publications

(7 citation statements)

References 4 publications

(4 reference statements)

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“…There is an exponential increase in the number of comparators; hence, the circuit requires large chip area, high bandwidth, and more power consumption. Another important area of 5-bit flash ADC is in the application of orthogonal frequency division multiplexing ultrawide band systems [17][18][19][20][21]. There has been much work in implementation of low power and high speed encoders for the design of the flash ADC.…”

Section: Introductionmentioning

confidence: 99%

Implementation of Power Efficient Flash Analogue-to-Digital Converter

Lakshmi

Srinivasulu

Pittala

2014

Active and Passive Electronic Components

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An efficient low power high speed 5-bit 5-GS/s flash analogue-to-digital converter (ADC) is proposed in this paper. The designing of a thermometer code to binary code is one of the exacting issues of low power flash ADC. The embodiment consists of two main blocks, a comparator and a digital encoder. To reduce the metastability and the effect of bubble errors, the thermometer code is converted into the gray code and there after translated to binary code through encoder. The proposed encoder is thus implemented by using differential cascade voltage switch logic (DCVSL) to maintain high speed and low power dissipation. The proposed 5-bit flash ADC is designed using Cadence 180 nm CMOS technology with a supply rail voltage typically ±0.85 V. The simulation results include a total power dissipation of 46.69 mW, integral nonlinearity (INL) value of −0.30 LSB and differential nonlinearity (DNL) value of −0.24 LSB, of the flash ADC.

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Section: Introductionmentioning

confidence: 99%

Implementation of Power Efficient Flash Analogue-to-Digital Converter

Lakshmi

Srinivasulu

Pittala

2014

Active and Passive Electronic Components

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“…The three key parameters for an ADC are resolution, speed and power consumption which cannot be changed once an ADC is designed [2]. Although flash ADC architecture is the fastest among known ADC architectures but it is limited to lower resolution due to large number of components and high power dissipation whose design requires 2 n -1 comparators for an n-bit ADC [1].…”

Section: Introductionmentioning

confidence: 99%

4-6 Bit Variable Resolution ADC

Varshney¹,

Goswami

Singh

2013

2013 International Symposium on Electronic System Design

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A low power variable resolution analog-to-digital converter (ADC) architecture has been proposed in a 45-nm CMOS technology. The design uses only 6 comparators for achieving the required conversion and thus saves huge amount of area in comparison to conventional flash ADC (which requires 2 n comparators for same bits). The proposed ADC when designed for 4 -6 bits, exhibit a SNR of 35.9 dB and SNDR of 35.4 dB and achieves a maximum speed of 1.4 GS/s. The ADC dissipates 80 µW, 96 µW and 1.15mW power for 4, 5 and 6 bits respectively.

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“…While [8] shows approximately linear scaling of power with resolution, the behaviour of [7] is super-linear since the number of amplifier stages in the comparator is tripled when switching from 8 bit to 12 bit resolution. ADCs with exponential power scaling were reported in [9][10][11]. In [9,10], flash ADCs were presented with a limited resolution variation between 5 and 8 bit, and in [11] a double architecture pipeline/Sigma-Delta ADC with a 6-16 bit variable resolution was demonstrated.…”

Section: Introductionmentioning

confidence: 99%

“…ADCs with exponential power scaling were reported in [9][10][11]. In [9,10], flash ADCs were presented with a limited resolution variation between 5 and 8 bit, and in [11] a double architecture pipeline/Sigma-Delta ADC with a 6-16 bit variable resolution was demonstrated.…”

Section: Introductionmentioning

confidence: 99%

A power-adaptable A/D converter with integrated data compression

Elneel

Aksoy

Schroeder

2010

Analog Integr Circ Sig Process

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A novel adaptable analog/digital converter (ADC) that combines analog/digital conversion and entropycoding for integrated data compression and low-power operation is reported. The converter has high flexibility of operation in terms of adaptable resolution, conversion rate and input signal statistics. This feature allows to adaptively react to changes of the situation and to put the device in each case into the optimum configuration. The ADC has been realized in a 0.6 lm CMOS technology with a peak resolution of 12 bit and 200 kS/s maximum sampling rate. A comprehensive power model of the converter is presented that reflects precisely the power consumption determined from experiments. The model is very useful for optimizing the converter configuration in the node of a wireless sensor network for specific situations. A feasible real-life application is demonstrated.

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A power and resolution adaptive flash analog-to-digital converter

Cited by 5 publications

References 4 publications

Implementation of Power Efficient Flash Analogue-to-Digital Converter

Implementation of Power Efficient Flash Analogue-to-Digital Converter

4-6 Bit Variable Resolution ADC

A power-adaptable A/D converter with integrated data compression

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