A post-processing approach to minimize TSV number for high-level synthesis of 3D ICs

Lee, Chih‐Hung; Huang, Tsorng-Yu; Cheng, Chun-Hua; Huang, Shih-Hsu

doi:10.1109/3ca.2010.5533773

Cited by 4 publications

(3 citation statements)

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“…We modified the object function and constraints from the previous work of Lee et al [6]. Some of the constraints including (1),(2),(3),(4),(5),(6) are the same with that of [3][6], and others were designed by us for the purpose of simultaneous resource duplication, resource binding and layer assignment.…”

Section: B Ilp Formulations For Tsv Number Minimizationmentioning

confidence: 99%

“…Krishnan and Katkoori [5] proposed a framework to integrate the resource binding and floorplaning problems together in the 3D ICs structure. Lee et al [6][7] also proposed an integer linear programming model for high-level synthesis of 3D ICs, and guarantee to get the optimal solution for the number of TSVs under the resources and footprint area constrains.…”

Section: Introductionmentioning

confidence: 99%

“…In this paper, we propose a resource duplication approach to overcome this resources usage problem in high-level synthesis of 3D ICs. By modifying and extension of the integer linear programming model proposed by Lee et al [6], our model can fully utilize the footprint area of 3D ICs structure to further reduce the number of TSVs without increasing the footprint area.…”

Section: Introductionmentioning

confidence: 99%

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A resource binding technique for TSV number minimization in high-level synthesis of 3D ICs

Cheng

Yen

2011

2011 International Symposium on Integrated Circuits

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Three dimensional integrated circuits allow multiple devices to be stacked on multiple layers. Therefore, utilize the area of each layer efficiently and minimize the number of through silicon vias (TSVs) are crucial to the 3D IC design. In this paper, we propose an integer linear programming (ILP) model to perform simultaneous resource binding and layer assignment in high-level synthesis of 3D ICs. Our objective is to minimize the number of TSVs under both the layer number constraint and the footprint area constraint. By means of duplicating hardware resources properly during resource binding and layer assignment, our approach has obvious improvement in reducing the number of TSVs while not increasing the footprint area. Experimental results show that our methodology is effective indeed for this 3D ICs synthesis problem.

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Section: B Ilp Formulations For Tsv Number Minimizationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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