A pipelined ROM-less architecture for sine-output direct digital frequency synthesizers using the second-order parabolic approximation

Sodagar, Amir M.; Lahiji, G.R.

doi:10.1109/82.964999

Cited by 45 publications

(13 citation statements)

References 14 publications

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“…Ashrafi et al [16] proposed an FPGA-based method that utilizes Chebyshev polynomial series interpolation. The developed technique unifies the results of ROM-less polynomial approximation methods for sinusoidal DDFS implemented on FPGAs [17]- [18]. Among various approximation techniques, Chebyshev polynomials are usually preferred for hardware implementation.…”

Section: B Function Approximation Paradigmsmentioning

confidence: 99%

Direct command generation methods for servo-motor drives

Yaman

Mutlu

Dölen

et al. 2009

2009 International Conference on Electrical Machines and Systems

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This study focuses on advanced direct command generation paradigms that can be easily incorporated to modern servo-motor drive systems. As an alternative to conventional methods, two new command generation techniques are proposed in this paper. In the first method, higher-order differences of a given trajectory (i.e. position) are computed and the resulting data are compressed via lossless data compression techniques. Besides conventional approaches, a novel compression algorithm is also introduced in the paper. With respect to the second method, the command trajectory is first divided into segments according to the inflection points. The segments are then approximated using various polynomial techniques. The sequence originating from modeling error is included to the generated series. These two command generation techniques are then implemented using Field Programmable Gate Arrays (FPGAs) and their performances are evaluated according to the resources used in FPGAs and the speed of computation.

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Section: B Function Approximation Paradigmsmentioning

confidence: 99%

Direct command generation methods for servo-motor drives

Yaman

Mutlu

Dölen

et al. 2009

2009 International Conference on Electrical Machines and Systems

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“…For the evaluation, the most used factor which evaluates the performances of direct digital synthesizer is the Spurious free dynamic range (SFDR) [8], [12]. This value represents the ratio of the power in the fundamental frequency, S, to power of the largest spurious signal, R, regardless of where it falls in the frequency spectrum.…”

Section: Simulink Implementation and Evaluation Of The Wave Arithmetimentioning

confidence: 99%

Referenced Approximation Technique for a Rom-Less Sweep Frequency Synthesizer

Jbari¹,

Bellarbi²,

Errachid³

2016

IJECE

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The main goal of this paper is to present a novel ROM-less direct digital frequency synthesizer for sweep instrumentation systems. It provides a main sweep channel for frequency analysis and a reference channel for phase and amplitude measurement block operating at constant frequency. For phase to amplitude converter, we propose a new trigonometric approximation technique based on a set of reference angles. In addition, we present the design of the proposed synthesizer and its evaluation in Matlab-Simulink environment. The simulation results illustrate the performances and demonstrate the effectiveness of our proposed circuit.

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“…The latency is proportional to the word length of phase accumulator. In [10] using first order parabolic approximation high performance DDFS has been designed and implemented in VLSI with maximum amplitude error of 0.8X10-4. As an extension of this work X. Li [11] proposes DDFS based on one fourth-order parabolic approximation.…”

Section: Introductionmentioning

confidence: 99%

A novel low-latency, high-speed DDFS architecture

Hatai

Chakrabarti

2010

2010 Annual IEEE India Conference (INDICON)

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A recent trend in the research of ROM-less DDFS architecture, which is endowed with high speed, low power and high SFDR features and will generate the sine or cosine waveforms within a broad frequency range. In this work one high-speed, low-power, and low-latency (requires 11 clock cycles) pipelined ROM-less DDFS has been proposed and implemented in Xilinx Virtex-II Pro FPGA. The proposed ROM-less DDFS design has 32 bit phase input and 16 bit amplitude resolution with maximum amplitude error of u 4 1.5 10 . The FPGA implementation of the proposed design has an SFDR of -94.3 dBc and maximum operation frequency of 276 MHz by consuming only 22 K gate and 1.05 mW/MHz power. The high speed of operation and low power makes the propose design suitable for the use in communication transceiver for the up and down conversion..

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A pipelined ROM-less architecture for sine-output direct digital frequency synthesizers using the second-order parabolic approximation

Cited by 45 publications

References 14 publications

Direct command generation methods for servo-motor drives

Direct command generation methods for servo-motor drives

Referenced Approximation Technique for a Rom-Less Sweep Frequency Synthesizer

A novel low-latency, high-speed DDFS architecture

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