A pipelined asynchronous 8051 soft-core implemented with Balsa

Chen, Chang-Jiu; Cheng, Wei-Min; Tsai, Ruei-Fu; Tsai, Hung-Yue; Wang, Tuan-Chieh

doi:10.1109/apccas.2008.4746187

Cited by 7 publications

(2 citation statements)

References 14 publications

(10 reference statements)

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“…PA8051 [110] is a pipelined asynchronous 8051 soft-core microcontroller implemented in description language Balsa. Its design consists of 5-stage pipeline as shown in fig.…”

Section: ) Pa8051mentioning

confidence: 99%

Towards Designing Asynchronous Microprocessors: From Specification to Tape-Out

et al. 2019

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Proceeding miniaturization in the VLSI circuits continues to pose challenges to the conventionally used synchronous design style in microprocessors. These include the distribution of clock in the GHz range, robustness to delay variations, reduction in electromagnetic interference, and energy conservation, to name a few. The asynchronous logic has been known for its ability to address the aforementioned challenges by means of the closed-loop handshake protocols, instead of notorious clock signals. Because of these advantages, there have been numerous attempts on building general and special purpose microprocessors during the last three decades. Still, however, the number of asynchronous processors commercially available is scarce, mainly due to an insufficient electronic design and automation tools support, an ambiguous design flow and testing mechanisms for asynchronous logic and, most importantly, absence of a forum to look for relevant works, explaining the design steps and tools for such microprocessors. This paper is intended to bridge this gap by 1) reviewing the design principles of asynchronous logic, including classification, signaling conventions, and pipelining approaches; 2) presenting the complete design flow and available electronic design and automation tools; 3) developing an encyclopedia of various general and special purpose microprocessors proposed by far; and 4) presenting an evaluation of those works in terms of area on the die and performance metrics. This paper will also serve as guidelines for the asynchronous microprocessor design and implementation in all phases from specification to tape-out.INDEX TERMS Asynchronous logic, electronic design and automation, microprocessor.

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“…PA8051 [110] is a pipelined asynchronous 8051 soft-core microcontroller implemented in description language Balsa. Its design consists of 5-stage pipeline as shown in fig.…”

Section: ) Pa8051mentioning

confidence: 99%

Towards Designing Asynchronous Microprocessors: From Specification to Tape-Out

et al. 2019

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“…The microprocessor 8051 has been still widely applied in industry since its announcement in 1980 [1][2][3][4][5][6][7][8][9][10][11][12][13]. That is why many microprocessor-related courses still open in electrical fields in Universities around the world.…”

Section: Introductionmentioning

confidence: 99%

A Microprocessor-Based Monitoring and Control System via Internet in Case Study of Pet Care

Lin

Liu

Pai

2011

AMR

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Since the past years, the microprocessor (8051) has been still playing an indispensable role as a controller in industry applications because of fast executing process, low-cost, small size and low power consumption, etc. It, however, usually lacks of long distance transmission, graphical interface and vision. On the other hand, VB is now a very popular software package for graphical interface design due to easy exploring and low price. Combining both superiorities as above, this paper develops a remote visional microprocessor-based monitoring and control platform using VB graphical interface. The nearby PC (server) can collect real-time sensing signals from the 8051 through RS232 and transmit it to remote PCs (client) for on line monitoring mechanism via Internet. Also, the client can send the control signals to the server and thus control the 8051. The real-time case study for feeding care in the Pet House is provided to verify its well performance and remote Web-based capability in term of fast, simple and robust performance.

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