A Pipelined 8x8 2-D Forward DCT Hardware Architecture for H.264/AVC High Profile Encoder

Silva, Thaísa Leal da; Diniz, Cláudio M.; Vortmann, João Alberto; Agostini, Luciano; Susin, Altamiro; Bampi, Sérgio

doi:10.1007/978-3-540-77129-6_5

Cited by 7 publications

(10 citation statements)

References 13 publications

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“…The latency for [11,28] were not reported. However, these schemes use 2-D 8 × 8 DCT coding that is similar to the DCT implementations presented in [31,32]. As a result, the latency for [11,28] is estimated to be in the range from 92 to 144 (from [31,32] resp.).…”

Section: Parallel To Serial Converter (P2s)mentioning

confidence: 99%

“…However, these schemes use 2-D 8 × 8 DCT coding that is similar to the DCT implementations presented in [31,32]. As a result, the latency for [11,28] is estimated to be in the range from 92 to 144 (from [31,32] resp.). Compared to all these existing designs, the proposed scheme has a latency of 1 cc which is the lowest.…”

Section: Parallel To Serial Converter (P2s)mentioning

confidence: 99%

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Lossless and Low-Power Image Compressor for Wireless Capsule Endoscopy

Khan

Wahid

2011

VLSI Design

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We present a lossless and low-complexity image compression algorithm for endoscopic images. The algorithm consists of a static prediction scheme and a combination of golomb-rice and unary encoding. It does not require any buffer memory and is suitable to work with any commercial low-power image sensors that output image pixels in raster-scan fashion. The proposed lossless algorithm has compression ratio of approximately 73% for endoscopic images. Compared to the existing lossless compression standard such as JPEG-LS, the proposed scheme has better compression ratio, lower computational complexity, and lesser memory requirement. The algorithm is implemented in a 0.18 μm CMOS technology and consumes 0.16 mm × 0.16 mm silicon area and 18 μW of power when working at 2 frames per second.

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Section: Parallel To Serial Converter (P2s)mentioning

confidence: 99%

Section: Parallel To Serial Converter (P2s)mentioning

confidence: 99%

Lossless and Low-Power Image Compressor for Wireless Capsule Endoscopy

Khan

Wahid

2011

VLSI Design

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“…Another FPGA implementation of an algebraic integer quantization approach to computing the 8×8 TRANSFROM was presented in (Wahid et al, 2006). (Silva et al, 2007) proposed high-throughput architecture of the forward 8×8 transform to encode high-definition videos in real time with a latency of 5 clock cycles to process 1D transform. This architecture was synthesized in FPGA with a minimum period of 8.13ns and in a TSMC 0.35µm CMOS standard cell technology leading to a period of 8.05ns.…”

Section: Forward and Inverse 8×8 Transformmentioning

confidence: 99%

“…The low power consumption is because the circuit works at quite low speed (27MHz). A pipeline 8×8 2D forward transform architecture is proposed which is capable of consuming and producing one sample per clock cycle in (Silva et al, 2007). It uses two 1-D transform processors and transpose RAM with a latency of 144 clock cycles.…”

Section: Asic Implementation and Comparisonsmentioning

confidence: 99%

Variable Bit-Depth Processor for 8×8 Transform and Quantization Coding in H.264/AVC

Ruiz¹,

Michell²

2011

Recent Advances on Video Coding

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“…In [8] four units in parallel process 4 Â 4 and 8Â 8 transforms in a common architecture at low latency and power. The pipelined design described in [9] computes one sample each clock cycle. An interesting high-throughput and cost-effective implementation of six different integer transforms based on a shared hardware is described in [10].…”

Section: Introductionmentioning

confidence: 99%