A Physical and SPICE Mobility Degradation Analysis for NBTI

Chaudhary, Ankush; Mahapatra, S.

doi:10.1109/ted.2013.2259493

Cited by 20 publications

(8 citation statements)

References 22 publications

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“…The growing concern of device failure due to NBTI has prompted a significant effort on the part of the research community, including but not limited to the content shown in Figure 1. For example, the aging measurement method [6][7][8][9] does not appear in Figure 1, which also belongs to the aging domain.…”

Section: Literature Review On Nbti Degradation Researchmentioning

confidence: 99%

A Learning-Based Framework for Circuit Path Level NBTI Degradation Prediction

2020

Electronics

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Negative bias temperature instability (NBTI) has become one of the major causes for temporal reliability degradation of nanoscale circuits. Due to its complex dependence on operating conditions, it is a tremendous challenge to the existing timing analysis flow. In order to get the accurate aged delay of the circuit, previous research mainly focused on the gate level or lower. This paper proposes a low-runtime and high-accuracy machining learning framework on the circuit path level firstly, which can be formulated as a multi-input–multioutput problem and solved using a linear regression model. A large number of worst-case path candidates from ISCAS’85, ISCAS’89, and ITC’99 benchmarks were used for training and inference in the experiment. The results show that our proposed approach achieves significant runtime speed-up with minimal loss of accuracy.

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Section: Literature Review On Nbti Degradation Researchmentioning

confidence: 99%

A Learning-Based Framework for Circuit Path Level NBTI Degradation Prediction

2020

Electronics

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“…It is important to exactly model the mobility degradation due to NBTI for NBTI-aware design. The modeling of mobility degradation has been studied in two previous works [Ayala et al 2011;Chaudhary and Mahapatra 2013]. Additionally, NBTI degradation in p-MOSFET devices is known to generate a decrement in the static noise margin of SRAM cells, resulting in cell stability problems due to read operations [Kumar et al 2006].…”

Section: Nbti Mechanismsmentioning

confidence: 99%

Lifetime Reliability Enhancement of Microprocessors

Hong

Lim

et al. 2015

ACM Comput. Surv.

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Ensuring lifetime reliability of microprocessors has become more critical. Continuous scaling and increasing temperatures due to growing power density are threatening lifetime reliability. Negative bias temperature instability (NBTI) has been known for decades, but its impact has been insignificant compared to other factors. Aggressive scaling, however, makes NBTI the most serious threat to chip lifetime reliability in today's and future process technologies. The delay of microprocessors gradually increases as time goes by, due to stress and recovery phases. The delay eventually becomes higher than the value required to meet design constraints, which results in failed systems. In this article, the mechanism of NBTI and its effects on lifetime reliability are presented, then various techniques to mitigate NBTI degradation on microprocessors are introduced. The mitigation can be addressed at either the circuit level or architectural level. Circuit-level techniques include design-time techniques such as transistor sizing and NBTI-aware synthesis. Forward body biasing, and adaptive voltage scaling are adaptive techniques that can mitigate NBTI degradation at the circuit level by controlling the threshold voltage or supply voltage to hide the lengthened delay caused by NBTI degradation. Reliability has been regarded as something to be addressed by chip manufacturers. However, there are recent attempts to bring lifetime reliability problems to the architectural level. Architectural techniques can reduce the cost added by circuit-level techniques, which are based on the worst-case degradation estimation. Traditional low-power and thermal management techniques can be successfully extended to deal with reliability problems since aging is dependent on power consumption and temperature. Self-repair is another option to enhance the lifetime of microprocessors using either core-level or lower-level redundancy. With a growing thermal crisis and constant scaling, lifetime reliability requires more intensive research in conjunction with other design issues. ACM Reference Format:Hyejeong Hong, Jaeil Lim, Hyunyul Lim, and Sungho Kang. 2015. Lifetime reliability enhancement of microprocessors: Mitigating the impact of negative bias temperature instability.

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“….options numdgt=8 reltol=0.01 itl2=120 stepgmin gmin=1e-16 .FUNC Not() {1.44e10*pwr(TIME/3600,0.25)} .FUNC Nit() {3.4e9*pwr(TIME/3600,0.18)} E1 1 0 VALUE={-4.63e-12*(Not()+Nit())} .TRAN 1 759600 uic .probe v(1,0) .print tran v(1,0) .SAVEBIAS "napon.bsp" TRAN TIME=759600 .END PSPICE model of PMOS transistor in subcircuit of IRF9520 [10] transistor which is modeled:…”

Section: Appendixmentioning

confidence: 99%

“…Despite the continuous study of NBTI effects and recognition of their impact on the electrical characteristics of MOS transistors, mechanisms responsible for these degradations are still not completely known. This is the reason why many scientists are nowadays oriented to the intensive investigation of the NBTI in MOS transistors [8] - [10].…”

Section: Introductionmentioning

confidence: 99%

Modeling and PSPICE simulation of NBTI effects in VDMOS transistors

et al. 2015

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In this paper the results of modeling and simulation of NBTI effects in p-channel power VDMOS transistor have been presented. Based on the experimental results, the threshold voltage shifts and changes of transconductance during the NBT stress have been modeled and implemented in the PSPICE model of the IRF9520 transistor. By predefining the threshold voltage value before the NBT stress, and by assigning the stress time, transfer characteristics of the transistor are simulated. These characteristics are within (1.33÷11.25)% limits in respect to the measured ones, which represents a good agreement.

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A Physical and SPICE Mobility Degradation Analysis for NBTI

Cited by 20 publications

References 22 publications

A Learning-Based Framework for Circuit Path Level NBTI Degradation Prediction

A Learning-Based Framework for Circuit Path Level NBTI Degradation Prediction

Lifetime Reliability Enhancement of Microprocessors

Modeling and PSPICE simulation of NBTI effects in VDMOS transistors

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