A Phase Behavior Aware Dynamic Cache Partitioning Scheme for CMPs

Liao, Xiaofei; Guo, Rentong; Yu, Dao‐Yi; Jin, Hai; Li, Lin

doi:10.1007/s10766-014-0334-5

Cited by 7 publications

(6 citation statements)

References 22 publications

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“…In particular, in this work we use phase-change detection to select the best cache partitioning scheme. We have devised an approach to detect phase changes based on the method proposed by Liao et al [14], Interval Coefficient of Variation (ICOV), as part of an online phase detection scheme that guides dynamic L2 cache partitioning, implemented using page coloring. ICOV was chosen for two main reasons, simplicity and effectiveness, as well as due to hardware constraints since only four hardware performance counters are available in our processor.…”

Section: Detecting Phase Changesmentioning

confidence: 99%

“…We found 20% as the best performing threshold for our proposal and platform. See [14] for further details.…”

Section: Detecting Phase Changesmentioning

confidence: 99%

“…In this example mix, KPart assigns firstly mcf_06 too little space (1 way), which damages its performance considerably. In the following cache disposal (that is, clustering applications in CLOS and assigning them cache ways), it is placed together with soplex_06 in a CLOS with a high number of ways (14). However, as shown in the characterization study, problematic applications (mcf_06 in this example) tend to occupy and waste a high portion of their allocated LLC space.…”

Section: Comparing Cpa With Kpartmentioning

confidence: 99%

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Phase-Aware Cache Partitioning to Target Both Turnaround Time and System Performance

Pons

Sahuquillo

Selfa

et al. 2020

IEEE Trans. Parallel Distrib. Syst.

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The Last Level Cache (LLC) plays a key role in the system performance of current multi-cores by reducing the number of long latency main memory accesses. The inter-application interference at this shared resource, however, can lead the system to undesired situations regarding performance and fairness. Recent approaches have successfully addressed fairness and turnaround time (TT) in commercial processors. Nevertheless, these approaches must face sustaining system performance, which is challenging. This work makes two main contributions. LLC behaviors regarding cache performance, data reuse and cache occupancy, that adversely impact on the final performance are identified. Secondly, based on these behaviors, we propose the Critical-Phase Aware Partitioning Approach (CPA), which reduces TT while sustaining (and even improving) IPC by making an effective use of the LLC space. Experimental results show that CPA outperforms CA, Dunn and KPart state-of-the-art approaches, and improves TT (over 40% in some workloads) over Linux default behavior while sustaining or even improving IPC by more than 3% in several mixes.

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Section: Detecting Phase Changesmentioning

confidence: 99%

“…We found 20% as the best performing threshold for our proposal and platform. See [14] for further details.…”

Section: Detecting Phase Changesmentioning

confidence: 99%

Section: Comparing Cpa With Kpartmentioning

confidence: 99%

See 1 more Smart Citation

Phase-Aware Cache Partitioning to Target Both Turnaround Time and System Performance

Pons

Sahuquillo

Selfa

et al. 2020

IEEE Trans. Parallel Distrib. Syst.

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show abstract

“…Lin et al [2008] evaluate several policies and metrics to guide the partitioning and find similar results in terms of overhead. Liao et al [2014] investigate how to identify application phases by means of miss-rate curves and IPC curves, and apply recoloring to adapt partitions to phases.…”

Section: Software Techniquesmentioning

confidence: 99%

A Software Cache Partitioning System for Hash-Based Caches

Scolari

Bartolini²,

Santambrogio

2016

ACM Trans. Archit. Code Optim.

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Contention on the shared Last-Level Cache (LLC) can have a fundamental negative impact on the performance of applications executed on modern multicores. An interesting software approach to address LLC contention issues is based on page coloring, which is a software technique that attempts to achieve performance isolation by partitioning a shared cache through careful memory management. The key assumption of traditional page coloring is that the cache is physically addressed. However, recent multicore architectures (e.g., Intel Sandy Bridge and later) switched from a physical addressing scheme to a more complex scheme that involves a hash function. Traditional page coloring is ineffective on these recent architectures. In this article, we extend page coloring to work on these recent architectures by proposing a mechanism able to handle their hash-based LLC addressing scheme. Just as for traditional page coloring, the goal of this new mechanism is to deliver performance isolation by avoiding contention on the LLC, thus enabling predictable performance. We implement this mechanism in the Linux kernel, and evaluate it using several benchmarks from the SPEC CPU2006 and PARSEC 3.0 suites. Our results show that our solution is able to deliver performance isolation to concurrently running applications by enforcing partitioning of a Sandy Bridge LLC, which traditional page coloring techniques are not able to handle. CCS Concepts: r Computer systems organization → Multicore architectures; r Software and its engineering → Main memory;

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“…We have devised an approach to detect phase changes based on the method proposed by Liao et al [136], Interval Coefficient of Variation (ICOV), as part of an online phase detection scheme that guides dynamic L2 cache partitioning, implemented using page coloring.…”

Section: Detecting Phase Changes Dynamicallymentioning

confidence: 99%

Interference Analysis and Resource Management in Server Processors: from HPC to Cloud Computing

Pons Escat

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Finalmente, quiero agradecer a las personas más importantes de mi vida, mi familia. A mis padres, gracias por inculcarme el valor del esfuerzo y enseñarme a sobreponerme a las adversidades. Pero sobretodo, por apoyarme en cada paso que doy y animarme en los momentos más difíciles. Vuestra sonrisa de orgullo es la mejor recompensa. A mis abuelos, por su amor infinito que siempre me da fuerzas. A mis hermanos mayores, con los que puedo contar siempre. A Julio y Miljana, por su apoyo y cariño, y al pequeño Julio que ha llenado la familia de felicidad. A Alfonso, por ser mi fiel compañero y estar siempre a mi lado. Y también a mi novio, Mario, por sacarme una sonrisa cuando más lo necesito. Gracias por motivarme a ser mejor cada día y perseguir mis sueños.

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A Phase Behavior Aware Dynamic Cache Partitioning Scheme for CMPs

Cited by 7 publications

References 22 publications

Phase-Aware Cache Partitioning to Target Both Turnaround Time and System Performance

Phase-Aware Cache Partitioning to Target Both Turnaround Time and System Performance

A Software Cache Partitioning System for Hash-Based Caches

Interference Analysis and Resource Management in Server Processors: from HPC to Cloud Computing

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