A PCM Voice Codec with On-Chip Filters

To deal with the wide dynamic rage necessary for a radio receiver or corresponding applications, but to avoid impractically high resolution at high data rates, the approach of using a floating-point analog-to-digital converter (FP-ADC) has been investigated. This approach de-links the dynamic range with the resolution, and a very wide dynamic range can be achieved by an ADC with a moderate resolution.The solution for an FP-ADC presented in this thesis is to amplify the input signal in several channels using binary weighted gains. The channel output with the largest amplitude, but still within the ADC input range, will be selected for conversion. The binary weighting is obtained by dividing the input signal with passive divider and amplifying the divider outputs by identical amplifiers. The outputs from the amplifiers are sampled individually. The selected sampled signal is then converted by a pipelined ADC. The result from the selection gives the exponent and the ADC output the mantissa of the floating-point number.Issues on the specific problems of designing the proposed FP-ADC have been addressed, including a general discussion about a pipelined ADC along with its sub-blocks.A thorough investigation of the distortion in a pipelined ADC due to static mismatches and systematic errors is also presented. The result of the investigation is a general approach on how to calculate the distortion in a pipelined ADC. The distortion analyses can be performed by both analytical methods and computer simulations.A chip has been manufactured in a standard analog 0.35 µm CMOS process giving 10 bits of resolution, and a dynamic range corresponding to a 15-bit ADC. The sampling rate is 54 Ms/s using 330 mW of power. This project started when Pietro Andreani talked me into pursuing PhD studies within the Electroscience department, and to investigate an interesting problem Jiren Yuan, my supervisor, presented. While being with the department my knowledge has been deepened and broadened within the area of mixed signal design, and especially data converters.I have also had lots of fruitful discussions with my colleagues at the department. By keeping up a friendly atmosphere and a high academic ceiling, it has been fun and well worth spending so many years at the same place. Especially I would like to mention Roland Strandberg, Martin Lantz, Martin Andersson and Gang Xu who have been there to discuss everything from transistors physics to amplifier design to intricate problems in data converters. I would like to thank them for their enthusiasm and help.I would also thank Anders "J" Johansson and Lars Olsson for taking their time to check my spelling and grammar and helping me make this thesis more readable.No thesis would have been possible without the work of Erik Jonsson or Stefan Molund, who are constantly keeping the computers, network and tools up running day and night.In addition to this, I would also like to thank all other parties who have been involved in this process. I cannot mention you all by name, but I will al...

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“…2-step charge-redistribution-DAC [32,33]. An array of binary weighted capacitors is used with a linear V-DAC.…”

Section: Logarithmic Successive Approximation Adcmentioning

confidence: 99%