A Passive UHF RFID Tag LSI with 36.6% Efficiency CMOS-Only Rectifier and Current-Mode Demodulator in 0.35/spl mu/m FeRAM Technology

Nakamoto, Hiroyuki; Yamamoto, Takuji; Kurata, H.; Yamada, Shinichi; Mukaida, K.; Ninomiya, Tamotsu; Ohkawa, Takenao; Masui, Shoichi; Gotoh, K.

doi:10.1109/isscc.2006.1696166

Cited by 54 publications

(27 citation statements)

References 3 publications

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“…So the condition of forward voltage will exist rarely. So the output voltage is obtained which is nearby equal to input voltage and get remarkable assortment of efficiency [30,31]. The switching or orientation of conducting of MOS transistors is well explained by schematic representation in the figures.…”

Section: Evaluation Of Mos Based Full-wave Centre-tapped Rectifier CImentioning

confidence: 99%

An Innovative Design: MOS Based Full-Wave Centre-Tapped Rectifier

Jain

Akashe

2016

Wireless Pers Commun

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A novel, more competent, low leakage and comparatively high speed full-wave centre-tapped rectifier is introduced with minimum distortion. Proficient and exploratory combinations of PMOS-PMOS or NMOS-NMOS logic are utilized to design full-wave centre-tapped rectifier. The scrupulous PMOS-PMOS logic with augmented stacked NMOS transistor is communal form of two PMOS and one NMOS transistor. The main motive of manipulating these circuits is to maintain the substrate biasing during circuit operation. The substrate biasing refers the exploitation in which substrate and drain/source terminal of a transistor is kept in reverse biasing mode. Due to utilization of modified MOS structure after replacing of diode, efficiency of full-wave centre-tapped rectifier is increased up to 20 % with compare to p-n junction diode based full wave centre-tapped rectifier and leakage power dissipation is reduced up to 57 %. The proposed circuit is designed to utilize the body effect properly to reduce the total leakage power of the circuit. The novelty of proposed circuit is the uniqueness of combination of MOS. Due to this; the proposed circuit has impressive resultant parameter with compare to other circuits and previous results. Proposed MOS based full-wave centre-tapped rectifier is optimized at 45 nm CMOS technology and cadence simulation experimental implementations of the leakage power and efficiency demonstrate better consistency through the proposed circuit.

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Section: Evaluation Of Mos Based Full-wave Centre-tapped Rectifier CImentioning

confidence: 99%

An Innovative Design: MOS Based Full-Wave Centre-Tapped Rectifier

Jain

Akashe

2016

Wireless Pers Commun

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“…Therefore, appropriate bias is needed to make the MOS transistor work in subthreshold region to improve the efficiency of rectification. The bias using voltage dividing with resistor can only achieve two stages rectifier cell stack [4], which can't provide high enough dc voltage when the input RF energy is small. Here we adopted switch capacitor circuit to provide dynamic bias for MOS transistor to achieve multi stage rectifier cell stack.…”

Section: A Cmos Uhf Rectifiermentioning

confidence: 99%

A novel RFID tag chip with temperature sensor in standard CMOS process

Zhang

Feng

Zhou

et al. 2010

Proceedings of 2010 IEEE International Symposium on Circuits and Systems

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This paper presents a novel RFID tag chip with temperature sensor in 0.18μm standard CMOS process. It consists of four blocks: RF/analog front-end circuit, 192-bit non-volatile memory (NVM), temperature sensor and digital baseband circuit. A CMOS UHF rectifier with dynamic bias using switch capacitor is proposed to improve the efficiency of rectification, while avoiding using costly Schottky diodes. We design a 192-bit NVM in standard CMOS process based on FN tunneling phenomenon with extremely small current density. It dissipates only 1.8μW/3.6μW for reading/writing operation. A 0.8μW smart temperature sensor with ±1 o C resolution without power hungry ADCs is achieved. As a result, the power consumption is 5.8μW, 6.8μW, and 8.6μW for reading sensor, reading NVM and writing NVM respectively. The chip core area is 0.6mm 2 in 0.18μm CMOS process.

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“…Nakamoto et al [8] implemented floating gate devices to preset the biasing voltage at the gates of MOSFETs, and Li et al [6] used off-chip high impedance resistor networks to provide different DC biasing voltages at the gates of the MOSFETs. Overall, these techniques effectively reduce the threshold voltage of the rectifying devices and improve the sensitivity of the harvester.…”

Section: Introductionmentioning

confidence: 99%

“…Overall, these techniques effectively reduce the threshold voltage of the rectifying devices and improve the sensitivity of the harvester. However, the discrete Si Schottky diodes [9] or the floating gate devices [8] are not fabricated in standard CMOS processes. Moreover, the techniques outlined in [8] and [6] need additional procedures to correctly program the biasing voltages, which will result in rising production costs.…”

Section: Introductionmentioning

confidence: 99%

An Ultra-Low-Power Integrated RF Energy Harvesting System in 65-nm CMOS Process

Liu

et al. 2015

Circuits Syst Signal Process

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In recent years, radio frequency (RF) energy harvesting systems have gained significant interest as inexhaustible replacements for traditional batteries in RF identification and wireless sensor network nodes. This paper presents an ultra-low-power integrated RF energy harvesting circuit in a SMIC 65-nm standard CMOS process. The presented circuit mainly consists of an impedance-matching network, a 10-stage rectifier with order-2 threshold compensation and an ultra-low-power power manager unit (PMU). The PMU consists of a voltage sensor, a voltage limiter and a capacitor-less low-dropout regulator. In the charge mode, the power consumption of the proposed energy harvesting circuit is only 97 nA, and the RF input power can be as low as −21.4 dBm (7.24 µW). In the burst mode, the device can supply a 1.0-V DC output voltage with a maximum 10-mA load current. The simulated results demonstrate that B Lian-xi Liu adam79416@126.com; Circuits Syst Signal Process the modified RF rectifier can obtain a maximum efficiency of 12 % with a 915-MHz RF input. The circuit can operate over a temperature range from −40 to 125 • C which exceeds the achievable temperature performance of previous RF energy harvesters in standard CMOS process.

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A Passive UHF RFID Tag LSI with 36.6% Efficiency CMOS-Only Rectifier and Current-Mode Demodulator in 0.35/spl mu/m FeRAM Technology

Cited by 54 publications

References 3 publications

An Innovative Design: MOS Based Full-Wave Centre-Tapped Rectifier

An Innovative Design: MOS Based Full-Wave Centre-Tapped Rectifier

A novel RFID tag chip with temperature sensor in standard CMOS process

An Ultra-Low-Power Integrated RF Energy Harvesting System in 65-nm CMOS Process

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