A Parametrizable Low-Power High-Throughput Turbo-Decoder

Prescher, G.; Gemmeke, Tobias; Noll, Tobias G.

doi:10.1109/icassp.2005.1416231

Cited by 37 publications

(26 citation statements)

References 11 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…In order to increase the throughput by a factor of P, an information block can be divided into P segments with equal length L and then each segment is processed independently by a dedicated MAP decoder [14,19,33,[40][41][42][43][44][45][46][47]. In this scheme, each of the P MAP cores processes the data sequentially and fetches/writes the data simultaneously always at the same offset x to each segment.…”

Section: Parallel Turbo Decoder Architecturementioning

confidence: 99%

Efficient hardware implementation of a highly-parallel 3GPP LTE/LTE-advance turbo decoder

Sun

Cavallaro

2011

Integration

View full text Add to dashboard Cite

a b s t r a c tWe present an efficient VLSI architecture for 3GPP LTE/LTE-Advance Turbo decoder by utilizing the algebraic-geometric properties of the quadratic permutation polynomial (QPP) interleaver. The highthroughput 3GPP LTE/LTE-Advance Turbo codes require a highly-parallel decoder architecture. Turbo interleaver is known to be the main obstacle to the decoder parallelism due to the collisions it introduces in accesses to memory. The QPP interleaver solves the memory contention issues when several MAP decoders are used in parallel to improve Turbo decoding throughput. In this paper, we propose a low-complexity QPP interleaving address generator and a multi-bank memory architecture to enable parallel Turbo decoding. Design trade-offs in terms of area and throughput efficiency are explored to find the optimal architecture. The proposed parallel Turbo decoder has been synthesized, placed and routed in a 65-nm CMOS technology with a core area of 8.3 mm 2 and a maximum clock frequency of 400 MHz. This parallel decoder, comprising 64 MAP decoder cores, can achieve a maximum decoding throughput of 1.28 Gbps at 6 iterations &

show abstract

Section: Parallel Turbo Decoder Architecturementioning

confidence: 99%

Efficient hardware implementation of a highly-parallel 3GPP LTE/LTE-advance turbo decoder

Sun

Cavallaro

2011

Integration

View full text Add to dashboard Cite

show abstract

“…For high throughput applications, it is necessary to use multiple SISO decoders working in parallel to increase the decoding speed. For parallel Turbo decoding, multiple SISO decoders can be employed by dividing a codeword block into several sub-blocks and then each sub-block is processed separately by a dedicated SISO decoder [7,20,30,41,42]. For LDPC decoding, the decoder parallelism can be achieved by employing multiple check node processors [10,14,32,40,49].…”

Section: Performancementioning

confidence: 99%

“…Compared to a dedicated LDPC decoder solution [37], this flexible decoder has only about 15-20% area overhead when normalized to the same throughput target (with the same number of iterations). Compared to a dedicated Turbo decoder solution [30], our flexible decoder shows only about 10-20% area overhead when normalized to the same technology and the same throughput and code length.…”

Section: Performancementioning

confidence: 99%

See 1 more Smart Citation

A Flexible LDPC/Turbo Decoder Architecture

Sun

Cavallaro

2010

J Sign Process Syst

View full text Add to dashboard Cite

Low-density parity-check (LDPC) codes and convolutional Turbo codes are two of the most powerful error correcting codes that are widely used in modern communication systems. In a multi-mode baseband receiver, both LDPC and Turbo decoders may be required. However, the different decoding approaches for LDPC and Turbo codes usually lead to different hardware architectures. In this paper we propose a unified message passing algorithm for LDPC and Turbo codes and introduce a flexible soft-input soft-output (SISO) module to handle LDPC/Turbo decoding. We employ the trellis-based maximum a posteriori (MAP) algorithm as a bridge between LDPC and Turbo codes decoding. We view the LDPC code as a concatenation of n super-codes where each super-code has a simpler trellis structure so that the MAP algorithm can be easily applied to it. We propose a flexible functional unit (FFU) for MAP processing of LDPC and Turbo codes with a low hardware overhead (about 15% area and timing overhead). Based on the FFU, we propose an area-efficient flexible SISO decoder architecture to support LDPC/Turbo codes decoding. Multiple such SISO modules can be embedded into a parallel decoder for higher decoding throughput. As a case study, a flexible LDPC/Turbo decoder has been synthesized on a TSMC 90 nm CMOS technology with a core area of 3.2 mm 2 . The decoder can support IEEE 802.16e LDPC codes, IEEE 802.11n LDPC codes, and 3GPP LTE

show abstract

“…The architecture can optimize the decoder and interleaver block to achieve the low power and high throughput. This can be obtained by the parallel interleaving [8] The design of parallel decoders can yield the reduced latency and increased throughput. To improve the efficient area, the foundation of large blocks are utilized [9].…”

Section: Introductionmentioning

confidence: 99%

Application of Fixed Point Turbo Decoding Algorithm for Throughput Enhancement of SISO Parallel Advanced LTE Turbo Decoders

Madhukumar¹,

Ramu²,

Veerasamy³

et al. 2017

IJIES

View full text Add to dashboard Cite

Turbo decoding for the advanced 4GPP-LTE wireless communication standard is the most challenging technique in terms of computational complexity and power consumption of corresponding cellular devices. The standard VLSI implementation of turbo decoder requires memory, latency, area, power, and throughput. These particularities cannot tolerate in some applications as well as the previous method of floating point has some pitfalls due to this; the performance is degraded. The novel fixed point technique for SISO parallel advanced long-term evolution turbo decoders with new hard-wried 6144 bit interleaver is proposed here to achieve the specification. The major contribution of the planned methodology is the enhancement of throughput in parallel SISO decoders by eliminating the critical data path problem in floating point method. The signal to noise ratio is calculated to reduce the power consumption, and zero state metrics are used to eliminate the bit error rate. The designed algorithms are used to enhance the error correction capacity.

show abstract

A Parametrizable Low-Power High-Throughput Turbo-Decoder

Cited by 37 publications

References 11 publications

Efficient hardware implementation of a highly-parallel 3GPP LTE/LTE-advance turbo decoder

Efficient hardware implementation of a highly-parallel 3GPP LTE/LTE-advance turbo decoder

A Flexible LDPC/Turbo Decoder Architecture

Application of Fixed Point Turbo Decoding Algorithm for Throughput Enhancement of SISO Parallel Advanced LTE Turbo Decoders

Contact Info

Product

Resources

About