A parallel technique for ATPG using genetic algorithms

Sabry, Mona; Wahba, Ayman; Mahdi, Hani

doi:10.1109/icm.1998.825571

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“…To understand the concepts of parallel technique in ATPG, [8] was referred. The paper mainly explained two things; one is the use of genetic algorithms and how parallelism can be used in ATPG.…”

Section: Introductionmentioning

confidence: 99%

Implementation of a Parallel Fault Simulation System using PODEM in a Hardware Accelerator using Python

K¹,

Palecha²

2021

JUSST

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VLSI Testing is one of the essential domains in recent times. With the channel length of the transistor decreasing continually, the number of transistors in a chip increases, thus increasing the probability of defects or faults. Automatic Test Pattern Generator is one way to find such input test vectors to the circuit, which will help identify the faults if present. PODEM algorithm is one such algorithm used in this regard. This paper helps in reducing the runtime of this algorithm by the parallelism approach. Different stuck-at faults in the gate level circuit are simulated parallelly.

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Section: Introductionmentioning

confidence: 99%