A Parallel State Assignment Algorithm for Finite State Machines

Abstract

Abstract. This paper summarizes the design and implementation of a parallel algorithm for state assignment of large Finite State Machines (FSMs). High performance CAD tools are necessary to overcome the computational complexity involved in the optimization of large sequential circuits. FSMs constitute an important class of logic circuits, and state assignment is one of the key steps in combinational logic optimization. The SMP-based parallel algorithm -based on the sequential program JEDI targeting multilevel logic implementation -scales nearly linearly with the number of processors for FSMs of varying problem sizes chosen from standard benchmark suites while attaining quality of results comparable to the best sequential algorithms.

XOR-FREE Implementation of Convolutional Encoder for Reconfigurable Hardware

“…With different viable approaches towards the state assignment, the heuristic seems to be the most promising [21]. The optimal state encoding methods require state assignment tools like NOVA [27] for area minimization of PLA implementations; JEDI [28] for multilevel implementations; Decomp; One Hot [23], and a lot more. These approaches are not promising while implementing state minimal convolution encoder with the fact that a significant source of dynamic power dissipation is modulo-two adders instead of shift registers.…”