A parallel parsing VLSI architecture for arbitrary context free grammars

Koulouris, A.; Koziris, Nectarios; Andronikos, Theodore; Παπακωνσταντίνου, Γ.; Tsanakas, Panayiotis

doi:10.1109/icpads.1998.741168

Cited by 2 publications

(1 citation statement)

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“…Other previous work includes a hardware-based implementation of an Early parser [Koulouris et al 1998]. Again, the space requirements for this tabledriven parsing algorithm make it unsuitable for network applications.…”

Section: Hardware-accelerated Parsersmentioning

confidence: 99%

Reconfigurable content-based router using hardware-accelerated language parser

Moscola

Lockwood

Cho³

2008

ACM Trans. Des. Autom. Electron. Syst.

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This article presents a dense logic design for matching multiple regular expressions with a field programmable gate array (FPGA) at 10+ Gbps. It leverages on the design techniques that enforce the shortest critical path on most FPGA architectures while optimizing the circuit size. The architecture is capable of supporting a maximum throughput of 12.90 Gbps on a Xilinx Virtex 4 LX200 and its performance is linearly scalable with size. Additionally, this article presents techniques for parsing data streams to provide semantic information for patterns found within a data stream. We illustrate how a content-based router can be implemented with our parsing techniques using an XML parser as an example. The content-based router presented was designed, implemented, and tested in a Xilinx Virtex XCV2000E FPGA on the FPX platform. It is capable of processing 32-bits of data per clock cycle and runs at 100 MHz. This allows the system to process and route XML messages at 3.2 Gbps.

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Section: Hardware-accelerated Parsersmentioning

confidence: 99%