A parallel MPEG-4 encoder for FPGA based multiprocessor SoC

Lehtoranta, O.; Salminen, Erno; Kulmala, Ari; Hännikäinen, Marko; Hämäläinen, Timo D.

doi:10.1109/fpl.2005.1515751

Cited by 22 publications

(9 citation statements)

References 10 publications

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“…System takes about 36 400 logic elements which is 88% of logic resources on Altera Stratix 1S40 FPGA. Furthermore, an MPEG-4 video encoder has been implemented on HIBI-based 4-processor system on a single FPGA [43]. In all cases, HIBI has met all the performance requirements with clear margin and enabled simple integration of system components.…”

Section: Performance Evaluationmentioning

confidence: 99%

HIBI Communication Network for System-on-Chip

Salminen

Kangas

Hämäläinen

et al. 2006

J VLSI Sign Process Syst Sign Image Video Technol

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This paper presents a communication network targeted for complex system-on-chip (SoC) and network-on-chip (NoC) designs. The Heterogeneous IP Block Interconnection (HIBI) aims at maximum efficiency and minimum energy per transmitted bit combined with quality-of-service (QoS) in transfers. Other features include support for hierarchical topologies with several clock domains, flexible scalability, and runtime reconfiguration of network parameters. HIBI is intended for integrating coarse-grain components such as intellectual property (IP) blocks that have size of thousands of gates. HIBI has been implemented in VHDL and SystemC and synthesized on several CMOS technologies and on FPGA. A 32-bit wrapper requires 5400 gates and runs with 315 MHz on 0.18 μm technology which shows that only minimal area overhead is paid for the advanced features. The area and frequency results are well comparable to other NoC proposals. Furthermore, data transfers are shown to approach the maximum theoretical performance for protocol efficiency. HIBI network is accompanied with a design framework with tools for optimizing the system through automated design space exploration.

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Section: Performance Evaluationmentioning

confidence: 99%

HIBI Communication Network for System-on-Chip

Salminen

Kangas

Hämäläinen

et al. 2006

J VLSI Sign Process Syst Sign Image Video Technol

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“…Research efforts have been made to address the efficiency problems of generalpurpose processors (including video decoding and encoding) in multimedia application. Various approaches have been explored to improve hardware efficiency, including specialized instructions [34], customized architectures [35], GPU offloading [36], application specific integrated circuit (ASIC) [37], and FPGA-based accelerators [38]. Computer clusters are a well-known configuration of distributed systems used to provide high-throughput computing.…”

Section: Related Workmentioning

confidence: 99%

VideoCoreCluster: Energy‐Efficient, Low‐Cost, and Hardware‐Assisted Video Transcoding System

Liu

Yoon

Kim

et al. 2018

Wireless Communications and Mobile Computing

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Video streaming is one of the killer applications in recent years. Video transcoding plays an important role in the video streaming service to cope with the various purposes. Specifically, content owners and publishers heavily utilize video transcoders to reconfigure source video in a variety of formats, video qualities, and bitrate to provide end users with the best possible quality of service. In this paper, we present VideoCoreCluster, a low-cost and energy-efficient transcoder cluster that is suitable for live streaming services. We designed and implemented real-time video transcoder cluster using cheap ($35), powerful, and energy-efficient Raspberry Pi. The quality of transcoded video provided by VideoCoreCluster is similar to the best software-based video transcoder while consuming significantly less energy (<3 W). We have proposed a scheduling algorithm based on priority of video stream and transcoding capacity. Our cluster manager provides reliable and scalable streaming services, because it uses the characteristics of adaptive bitrate scheme. We have deployed our transcoding cluster to provide IP-based TV streaming services on our university campus.

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“…Our parallel video encoder software is based on horizontal spatial parallelization [12]. Briefly, the application consists of a master processor (Nios) that controls the encoding flow, collects the bitstream, and handles the I/O, such as sending data back and forth with a PC via Ethernet.…”

Section: Mpeg-4 Applicationmentioning

confidence: 99%

Reliable GALS Implementation of MPEG-4 Encoder with Mixed Clock FIFO on Standard FPGA

Kulmala

Hämäläinen

Hännikäinen

2006

2006 International Conference on Field Programmable Logic and Applications

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Globally Asynchronous Locally Synchronous (GALS) is a paradigm for complexity management and re-use of large System-on-Chip (SoC) architectures.GALS is most often based on specific ASIC design components or special FPGA platforms with custom development tools. In this paper we present a multiprocessor GALS implementation on a standard commercial FPGA with standard development tools.The key building block is a novel, reliable RTL mixed clock FIFO. A complete MPEG-4 video encoder with four processors is implemented for proofing the concept. The area overhead compared to a fully synchronous design is shown to be only 2% and the performance overhead is 3%. This is negligible compared to the benefits that are much better flexibility, ASIC or FPGA vendor independency, and reduced design time. Furthermore, the mixed-clock interfaces allow easy re-usability, since the RTL-level blocks do not need to be re-verified in design iterations.

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A parallel MPEG-4 encoder for FPGA based multiprocessor SoC

Cited by 22 publications

References 10 publications

HIBI Communication Network for System-on-Chip

HIBI Communication Network for System-on-Chip

VideoCoreCluster: Energy‐Efficient, Low‐Cost, and Hardware‐Assisted Video Transcoding System

Reliable GALS Implementation of MPEG-4 Encoder with Mixed Clock FIFO on Standard FPGA

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