A Nyquist-rate pipelined oversampling A/D converter

Paul, Susanne; Lee, H.-S.; Goodrich, J.; Alailima, T.F.; Santiago, D.D.

doi:10.1109/4.808902

Cited by 11 publications

(2 citation statements)

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“…It has been found that power consumption of pipeline A/D converter decreased quency increased 360 mprovement of SFDR is approximately stagnant 0.127dB/month. This point is also to be noted that, we found considering more than 200 papers and books written on Pipeline A/D converter by approximately 580 authors that, among all these authers there is only one Female author named Susanne A. Paul [9]. …”

Section: Discussionmentioning

confidence: 84%

State-of-the-art pipeline A/D converter survey and analysis

Hussain

Zakir

Sheikh

2012

2012 International Conference on Informatics, Electronics &Amp; Vision (ICIEV)

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This paper surveys and analyzes state-of-the-art pipeline A/D Converter reported in IEEE from 1987 to June 2011, including performance comparison of these converters on the ground of Resolution, Sampling Rate, Power, Spurious Free Dynamic Range (SFDR), and Signal to Noise plus Distortion Ratio (SNDR)/ Signal to Noise and Distortion Ratio (SINAD). Technological and architectural progress brings low power, low voltage high sampling rate pipeline A/D converter though the resolution being constant over the period. We found that power consumption of pipeline A/D converter decreased 1.62mW/month, sampling frequency increased 360 KHz/month, improvement of SFDR is approximately stagnant, and SNDR decreased 0.127dB/month over the time.

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Section: Discussionmentioning

confidence: 84%

State-of-the-art pipeline A/D converter survey and analysis

Hussain

Zakir

Sheikh

2012

2012 International Conference on Informatics, Electronics &Amp; Vision (ICIEV)

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“…There have also been attempts at reducing the quantization noise over the entire Nyquist band, resulting in delta-sigma converters which do not require oversampling. This is accomplished either through parallel architectures [13] or pipeline architectures [14]. Both approaches rely on significantly increasing the analog hardware.…”

Section: High-performance Adcs At Low Oversampling Ratiosmentioning

confidence: 99%

Oversampled pipeline A/D converters with mismatch shaping

Shabra

Lee

2002

IEEE J. Solid-State Circuits

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This paper presents a pipeline analog-to-digital converter (ADC) with improved linearity. The linearity improvement is achieved through a combination of oversampling and mismatch shaping, which modulates the distortion energy out of band. Mismatch shaping can be realized in a traditional 1-bit/stage pipeline ADC, but the ADC's transfer characteristic properties limit its effectiveness at pushing the distortion out of band. These limitations can be alleviated by using a 1-bit/stage commutative feedback capacitor switching pipeline design. A test chip was fabricated in a 0.35-m CMOS process to demonstrate mismatch shaping. Experimental results obtained indicate that the spurious-free dynamic range improves by 8.5 dB to 76 dB when mismatch shaping is used at an oversampling ratio of 4 and a sampling rate of 61 MHz. The signal-to-noise and distortion ratio improves by 3 dB and the maximum integral nonlinearity decreases from 1.8 to 0.6 LSB at the 12-bit level.

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