2002
DOI: 10.1109/4.997849
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Oversampled pipeline A/D converters with mismatch shaping

Abstract: This paper presents a pipeline analog-to-digital converter (ADC) with improved linearity. The linearity improvement is achieved through a combination of oversampling and mismatch shaping, which modulates the distortion energy out of band. Mismatch shaping can be realized in a traditional 1-bit/stage pipeline ADC, but the ADC's transfer characteristic properties limit its effectiveness at pushing the distortion out of band. These limitations can be alleviated by using a 1-bit/stage commutative feedback capacito… Show more

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Cited by 19 publications
(4 citation statements)
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“…From the requirements of the test procedures, debugging the source requires the use of numerous bits than its digital multi [17,18]. Using KEITHLEY 2000 (6!-resolution) digital form as a detection device during debugging, the median topic design source is determined to be five and a half.…”
Section: Results Analysis and Discussionmentioning
confidence: 99%
“…From the requirements of the test procedures, debugging the source requires the use of numerous bits than its digital multi [17,18]. Using KEITHLEY 2000 (6!-resolution) digital form as a detection device during debugging, the median topic design source is determined to be five and a half.…”
Section: Results Analysis and Discussionmentioning
confidence: 99%
“…Device averaging techniques are ideally suited to over-sampling designs (OSR ≥ 2) with [8] achieving 100 dB SFDR for a 14-bit oversampled pipeline ADC using capacitor averaging techniques. Analog and digital background calibration techniques have also been used in the literature [9]- [12], but tend to consume higher power and area as a result of significant hardware redundancy. Dithering and mismatch-shaping [13] have also been used to design over-sampled pipeline ADCs, but effective bandwidth is reduced as a result of the oversampling, and additional logic is usually required to filter the out-of-band noise.…”
Section: Introductionmentioning
confidence: 99%
“…Self-calibration techniques [5][6][7] require some control logic and digital memories which significantly increase the chip area and power consumption. Other techniques reduce the sensibility to capacitor ratio using the so called ''capacitor error averaging'' [8][9][10]. However, these techniques do not remove completely the mismatch error, while the ratio independent techniques [11][12][13][14] do.…”
Section: Introductionmentioning
confidence: 99%