A novel W/WNx/dual-gate CMOS technology for future high-speed DRAM having enhanced retention time and reliability

Saino, K.; Kato, Yasuki; Kitamura, E.; Takaishi, Y.; Ando, M.; Taguwa, T.; Kanda, Takashi; Yamada, S.; Sekiguchi, Tomoko

doi:10.1109/iedm.2003.1269311

Cited by 10 publications

(9 citation statements)

References 4 publications

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“…PMOSFETs with P poly-Si gate, nitrided gate oxide and lightly doped drain structure were fabricated on n-well of p-Si(100) substrates using a standard CMOS process [9]. Plasma-nitrided SiON gate dielectric has a base SiO of 2.0 nm physical thickness and peak nitrogen concentration of 12% near the poly-Si/SiO interface, as estimated from secondary ion mass spectroscopy.…”

Section: Devices and Interface Trap Measurementmentioning

confidence: 99%

Enhancement of BTI degradation in pMOSFETs under high-frequency bipolar gate bias

Zhu

Nakajima

Ohashi³

2005

IEEE Electron Device Lett.

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Negative bias temperature (NBT) instability of p-MOSFETs with ultrathin SiON gate dielectric has been investigated under various gate bias configurations. The NBT-induced interface trap density (1 it ) under unipolar bias is essentially lower than that under static bias, and is almost independent of the stress frequency up to 10 MHz. On the contrary, 1 it underbipolar pulsed bias of frequency larger than about 10 kHz is significantly enhanced and exhibits a strong frequency dependence, which has faster generation rate and smaller activation energy as compared to other stress configurations. The degradation enhancement is attributed to the energy to be contributed by the recombination of trapped electrons and free holes upon the silicon surface potential reversal from accumulation to inversion.Index Terms-Dynamic stress, negative bias temperature instability (NBTI), pMOSFETs, recombination, ultrathin gate oxide.

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Section: Devices and Interface Trap Measurementmentioning

confidence: 99%

Enhancement of BTI degradation in pMOSFETs under high-frequency bipolar gate bias

Zhu

Nakajima

Ohashi³

2005

IEEE Electron Device Lett.

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“…To meet these demands, high-performance transistors are inevitable. Plasma-nitrided SiO has been proposed as the gate dielectrics for next-generation DRAMs [1]. However, with scaling of oxide thickness, the low nitrogen concentration in the oxynitride may result in an insufficient suppression of boron penetration due to the heavy thermal budget peculiar to the DRAM fabrication process, which leads to an undesired shift.…”

Section: Introductionmentioning

confidence: 99%

Atomic Layer-deposited Si-nitride/SiO/sub 2/ stack gate dielectrics for future high-speed DRAM with enhanced reliability

Nakajima

Ohashi²,

Zhu

et al. 2005

IEEE Electron Device Lett.

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Atomic layer-deposited (ALD) Si-nitride/SiO 2 stack gate dielectrics were applied to high-performance transistors for future scaled DRAMs. The stack gate dielectrics of the peripheral pMOS transistors excellently suppress boron penetration. ALD stack gate dielectrics exhibit only slightly worse negative-bias temperature instability (NBTI) characteristics than pure gate oxide. Enhanced reliability in NBTI was achieved compared with that of plasma-nitrided gate SiO 2. Memory-cell (MC) nMOS transistors with ALD stack gate dielectrics show slightly smaller junction leakage than those with plasma-nitrided gate SiO 2 in a high-drain-voltage region, and have identical junction leakage characteristics to transistors with pure gate oxide. MCs having transistors with ALD stack gate dielectrics and those with pure gate oxide have the identical retention-time distribution. Taking the identical hole mobility for the transistors with ALD stack gate dielectrics to that for the transistors with pure gate oxide both before and after hot carrier injection (previously reported) into account, the ALD stack dielectrics are a promising candidate for the gate dielectrics of future high-speed, reliable DRAMs.

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“…We refer to data extracted by Semiconductor Insight for the 1Gbit DDR3 die manufactured by Micron Technologies in a 78nm DRAM process for the area of the cell array and peripheral circuitry [15]. Table 1 lists additional information related to a complete 512MB DDR3 chip, and Table 2 summarizes the key parameters of a 32MB array block of one 512MB DDR3 chip.…”

Section: Dram Architecturementioning

confidence: 99%

“…The I/O and DRAM power signals also connect to the FPGA bonding pads. We assume the FPGA is fabricated with a 90nm CMOS process and the DRAM with a 78nm process using dual gate triple metal technology [15]. We estimate that two additional metal layers in the FPGA will route signals from the DRAM layer to their locations in the FPGA.…”

Section: Dram Architecturementioning

confidence: 99%

“…We can calculate the area of the tile width in comparison to pitch and copper bond size: pitch_width = bond_width + spacing_width (8) tile_width = 3 × bond_width + 2 × spacing_width (9) tile_height = 3 × bond_width + 2 × spacing_width (10) A tile = tile_width × tile_height (11) We make the following simplifying assumptions: bond_width = bond_height (12) spacing_width = spacing_height (13) num_horizontal_bonds = num_vertical_bonds (14) From these assumptions, we can replace Eq. (11) with (15) …”

Section: Morrow Et Al's [12]mentioning

confidence: 99%

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Using 3D integration technology to realize multi-context FPGAs

Cevrero¹,

Athanasopoulos²,

Parandeh-Afshar

et al. 2009

2009 International Conference on Field Programmable Logic and Applications

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This paper advocates the use of 3D integration technology to stack a DRAM on top of an FPGA. The DRAM will store future FPGA contexts. A configuration is read from the DRAM into a latch array on the DRAM layer while the FPGA executes; the new configuration is loaded from the latch array into the FPGA in 60ns (5 cycles). The latency between reconfigurations, 8.42μs, is dominated by the time to read data from the DRAM into the latch array. We estimate that the DRAM can cache 289 FPGA contexts.

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A novel W/WNx/dual-gate CMOS technology for future high-speed DRAM having enhanced retention time and reliability

Cited by 10 publications

References 4 publications

Enhancement of BTI degradation in pMOSFETs under high-frequency bipolar gate bias

Enhancement of BTI degradation in pMOSFETs under high-frequency bipolar gate bias

Atomic Layer-deposited Si-nitride/SiO/sub 2/ stack gate dielectrics for future high-speed DRAM with enhanced reliability

Using 3D integration technology to realize multi-context FPGAs

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