A novel video signal processor with programmable data arrangement and efficient memory configuration

In this paper, a low power full-search block matching (FSBM) motion estimation design for the H.263+ low bit rate video coding was proposed. The features of H.263+ such as half-pixel precision and some advanced modes (advance prediction mode, PB-frame mode and reduced resolution update mode) are taken into consideration. This architecture can deal with different block size and searching range in a single chip without any latency. We use a 1-D and 2-D mixed architecture to fulfill this goal. To achieve the purpose of low power and reduce the design period, we use dual supply voltage levels in this chip. This chip is realized by TSMC 0.6um single-poly triple-metal CMOS technology. The operation frequency is set at 60MHz to meet the requirement of the real time processing in the reduced resolution update mode in H.263+. The power consumption is 424mW at 60MHz and the throughput is 36 frames per second with CIF format at 60MHz.

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Efficient memory ip design for HDTV coding applications

Hsia

2003

IEEE Trans. Circuits Syst. Video Technol.

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The memory intellectual property (IP) is a key component for video coding systems as using system on one chip design methodology. In this paper, cost-effective memory design and complex address generation are presented for high-definition television coding applications. The addressing method uses a bit-allocation approach to simplify the computational circuit and significantly improves the memory access speed. For the bit-allocation requirement, a new memory structure is designed using pseudoaddress decoding concept to reduce the I/O complexity and to shorten the access time. The memory IP integrated to practical video coding systems is also presented. The experiments show that the proposed memory IP can provide better performance than the conventional one.

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A novel video signal processor with programmable data arrangement and efficient memory configuration

Cited by 5 publications

References 20 publications

Survey on Algorithm and VLSI Architecture for MPEG-Like Video Coder

Survey on Algorithm and VLSI Architecture for MPEG-Like Video Coder

Low power full-search block-matching motion estimation chip for H.263+

Efficient memory ip design for HDTV coding applications

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