Efficient memory ip design for HDTV coding applications

Hsia, Shih-Chang

doi:10.1109/tcsvt.2003.813418

Search citation statements

Order By: Relevance

Paper Sections

Select...

Vlsi Architecture and Chip Implementation1

Citation Types

Supporting

Mentioning

Contrasting

Year Published

2009

2016

Publication Types

Select...

Article3

Other2

Relationship

Self Cite0

Independent5

Authors

Journals

Cited by 12 publications

(1 citation statement)

References 18 publications

(13 reference statements)

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Thus we employ the temporal registers R0~R15 to store the pixels for data re-ordering. The memory access and addressing design can refer to our previous paper [17].…”

Section: Vlsi Architecture and Chip Implementationmentioning

confidence: 99%

Transposed-Memory Free Implementation for Cost-Effective 2D-DCT Processor

Hsia

Tsai

Wang

et al. 2009

J Sign Process Syst Sign Image Video Technol

View full text Add to dashboard Cite

This paper presents a cost-effective 2D-DCT processor based on a fast row/column decomposition approach. With a particular schedule, the processor does not require the transposed memory for 2D-DCT computing. We re-arrange the cosine coefficients of the first and second 1D-DCT transformations to keep DC-coefficient error free. The new architecture uses state-machines to generate cosine coefficients rather than ROM table, to save the memory cells and the address generator. For 8×8 DCT realization, the circuit only needs 36 adders without multipliers, and the whole chip uses about 19 k transistors. The chip area is about 4 mm 2 using TSMC 0.35 um CMOS process. The circuit complexity is only 1/3~1/5 of the conventional DCT chips.

show abstract

“…Thus we employ the temporal registers R0~R15 to store the pixels for data re-ordering. The memory access and addressing design can refer to our previous paper [17].…”

Section: Vlsi Architecture and Chip Implementationmentioning

confidence: 99%