A Novel Ultra-Low Power (ULP) Low Noise Amplifier using Differential Inductor Feedback

Shameli, A.; Heydari, Payam

doi:10.1109/esscir.2006.307603

Cited by 33 publications

(16 citation statements)

References 6 publications

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“…However, the NF of the CG LNA is considerably larger than that of the CMOS common-source or cascode LNAs. Previously employed in common-source LNAs in [5] and [6], the -boosting technique was proposed by [7] to improve the NF performance of a UWB CG LNA. On the other hand, recent advances in high-speed integrated circuits and continuous scaling of minimum feature sizes of silicon-based devices have increased the interest in on-chip implementation of transmission lines (TLs), which are key components of broadband distributed circuits.…”

Section: Introductionmentioning

confidence: 99%

Design and Analysis of a Performance-Optimized CMOS UWB Distributed LNA

Heydari

2007

IEEE J. Solid-State Circuits

127

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In this paper, the systematic design and analysis of a CMOS performance-optimized distributed low-noise amplifier (DLNA) comprising bandwidth-enhanced cascode cells will be presented. Each cascode cell employs an inductor between the common-source and common-gate devices to enhance the bandwidth, while reducing the high-frequency input-referred noise. The noise analysis and optimization of the DLNA accurately accounts for the impact of thermal noise of line terminations and all device noise sources of each CMOS cascode cell including flicker noise, correlated gate-induced noise and channel thermal noise on the overall noise figure. A three-stage performance-optimized wideband DLNA has been designed and fabricated in a 0.18-m SiGe process, where only MOS transistors were utilized. Measurements of the test chip show a flat noise figure of 2.9 dB, a forward gain of 8 dB, and input and output return losses below 12 dB and 10 dB, respectively, across the 7.5 GHz UWB band. The circuit exhibits an average IIP3 of 3.55 dBm. The 872 m 872 m DLNA chip consumes 12 mA of current from a 1.8-V DC voltage.

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Section: Introductionmentioning

confidence: 99%

Design and Analysis of a Performance-Optimized CMOS UWB Distributed LNA

Heydari

2007

IEEE J. Solid-State Circuits

127

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“…I mix is no longer shared between 1 (20/0.13) µm (W/L) 2 (30/0.13) µm (W/L) 3 (50/0.13) µm C tune 220 fF L pk 3.6 nF L g 10 nH R F 4 K switching and transductor stages, the sizing of M LOi becomes independent. In the circuit reported in Fig.…”

Section: Mixermentioning

confidence: 97%

“…This phenomenon represented by f T plays a key role in the optimization of RF building blocks. Also, the tradeoff between RF performances and the current consumption is better represented by the FOM RFLP proposed in the eq (1) [2]: …”

Section: Device Skills and Circuit Designmentioning

confidence: 99%

Micro-watt building blocks for biomedical RF tranceivers

Taris¹,

Kraimia²,

Bégueret³

et al. 2011

2011 Annual International Conference of the IEEE Engineering in Medicine and Biology Society

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The development of Wireless Body Area Network (WBAN) is a key point enabling the mobility health. Among the most critical constrains in WBAN implementation is the power consumption of wireless featuring nodes. This work focuses on the development of ultra low power radio building blocks dedicated to 2.4 GHz ISM band. A novel design approach based on device optimization is first presented. It is then applied to the implementation of a Low Noise Amplifier (LNA) and a mixer in a 0.13 μm CMOS technology. The LNA provides a 13.1 dB gain and a 5.3 dB NF for a 60 μW/0.4 V power consumption. The mixer achieves a conversion gain of 17.5 dB and a NF of 12 dB at 0 dBm LO power. It consumes 350 μW for a 0.8 V supply.

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“…We also note that, the commonsource input stage LNA (Park, et al, 2005), show a poor linearity performance, even with an ultra low-power made devices (Shameli & Heydari, 2006), suggesting that the trade-off between, conversion gain, noise figure, linearity, and power consumption could be relaxed, only when considering a multi-block design methodology, with distinct biasing circuits. …”

Section: Advanced Microwave Circuits and Systems 68mentioning

confidence: 99%

“…3.1 Dynamic Feedback LNA Several proposals were introduced lately for the design of low-power, UWB CMOS LNA (Park, et al, 2005), (Yu et al, 2006), (Shameli & Heydari, 2006), (Yo & Yoo, 2007). Due particularly to its low input impedance, the common-gate input LNA exhibits an excellent linearity, selectivity, and impedance matching over the common-base LNAs (Cusmai & Brandolini, 2006).…”

Section: Design Techniquesmentioning

confidence: 99%