A novel test structure for FEOL device CCTG CBCM measurement in advanced 28nm technology

Abstract

In the advanced CMOS technology nodes, overlap capacitance (Cov), gate fringing capacitance (Ct) and contact-to-gate capacitance (Cctg) have been increasingly important components of transistor parasitic. Accurate Cov could be extract from MOSFET Cgc curve with metal routing de-embedded structure. But Cf and Cctg could not be extracted and separated clearly with traditional AC testkey. Traditionally, Cctg and Cf are simulated and extracted by 3D solver such as Raphael simulator but lack of the correlation between Silicon and simulation. In this paper, we introduce CBCM into MOSFET FEOL Cctg and Cf measurement and extraction. With good capacitance measurement resolution of CBCM methodology and specially designed test structurers, Cctg and Cf can be successfully measured and extracted without mega routing of multiplier device.The test structures and extraction methodology are described in this paper, the extraction results from a 28nm process is also presented. This is the first published paper in MOSFET transistor FEOL parasitic (Cf+Cctg) measurement from 28nm process real Si. INTRO[)UCT]ONWith the advancement in CMOS technologies, transistor sizes have been shrinking to achieve high speed, low power and high density. The affect of parasitic capacitance in circuit simulation is more and more important. The major capacitance components [3] in the MOSFET device are gate plate to body capacitance (Cgg), gate to LDD overlap capacitance (Cov)[l], [2], junction capacitance (Cj, Cjsw, Cjswg) , gate fringing capacitance (Ct) and contact-to-gate capacitance (Cctg). The Cgg term could be easily measured and characterized from the traditional designed MOSFET transistor CV test structure such as plate gate MOSFET structure. 978-1-4673-1030-7/12/$31.00 ©2011 IEEE 248 CCTG Gate T CGG STI Cjswg STI Cjs S Cjs Fig. 1. shows the cross-sectional view of a MOSFET and the capacitances associated with the transistor, Transistor capacitances are denoted by Cgg (gate plate to body capacitance), gate to contact capacitance (Cctg), gate to LOO overlap capacitance (Cov), and gate to diffusion fringe component of the capacitance Cf. Cj, Cjsw and Cjswg could also be easily measured and extracted based on the diffusion large area, diffusion large peripheral multiplier structure and multiplier finger gate structure. But the others parasitic capacitance such as overlap capacitance (Cov), contact-to-gate capacitance (Cctg) and fringing capacitance (Ct) cannot be measured individually. Especially for contact-to-gate capacitance (Cctg), its ratio expected to increase dramatically when contact-to-gate spacing pushed below urn due to process shrink. It needs to decouple from CGD/CGS measurement which is combination of overlap capacitance (Cov) and fringe component (Ct). CONTACT-TO-GATE CAPACITANCE Foundry model always lump Cctg value into Cf parameters. These two parasitic capacitance model behavior or LPE extraction results cannot be easily measured and verified by a typical design testkey and CV measurement. Traditionally, they are generated by 3D ...