A new interconnect parasitic extraction flow considering geometry-related variation has been proposed in this letter. The 42 interconnect capacitance loads were fabricated by 55-nm process technology and measured to characterize geometric variation. According to the new extraction flow, interconnect technology file (ITF) has been optimized and established. As a result, both extracted error by layout parasitic extraction tool and simulated error by field solver have been improved obviously with this optimized ITF. Meanwhile, an on-chip interconnect test technique with nonoverlapping signal generation circuitry based on charge-induced-injection error-free charge-based capacitance measurement has been designed in this letter to simplify the test procedure.Index Terms-Geometric-related variation, interconnect parasitic extraction, charge-induced-injection error-free charge-based capacitance measurement (CIEF CBCM), non-overlapping signal generation circuitry.
This paper presents experimental RF characterizations and modeling on the nano-scale multi-finger gate MOSFETs of the HLMC 40 nm low-power CMOS technology. Both the resistive and capacitive components in the equivalent circuit model for the RF MOSFET devices are calibrated based on temperature-dependent S-parameter measurements (0.25 -40 GHz) from 298 K to 6 K. By integrating the intrinsic device model and the extrinsic parasitic parameters, a generic cryogenic device RF model is developed to capture the cutoff frequency and high-frequency performance of NMOS and PMOS transistors with varied device configurations. The establishment of validated database as functions of device size, temperature, and frequency responses lays a solid foundation for practical large-scale cryo-CMOS RF circuit design and optimization.
In this paper, the SPICE model of poly resistor is accurately developed based on silicon data. To describe the non-linear R-V trend, the new correlation in temperature and voltage is found in non-silicide poly-silicon resistor. A scalable model is developed on the temperature-dependent characteristics (TDC) and the temperature-dependent voltage characteristics (TDVC) from the R-V data. Besides, the parasitic capacitance between poly and substrate are extracted from real silicon structure in replacing conventional simulation data. The capacitance data are tested through using on-wafer charge-induced-injection error-free charge-based capacitance measurement (CIEF-CBCM) technique which is driven by non-overlapping clock generation circuit. All modeling test structures are designed and fabricated through using 40nm CMOS technology process. The new SPICE model of poly-silicon resistor is more accurate to silicon for analog circuit simulation.
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