A Novel System-on-Chip Architecture for Efficient Image Processing

Mariatos, V.; Adaos, K.D.; Alexiou, George

doi:10.1109/rsp.2008.33

Cited by 3 publications

(2 citation statements)

References 4 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…1) Cache architectures for structured data management: Cache architectures for general purpose processors have been optimised to deal with structured data and especially for multimedia applications [1], [5].However, to exploit the parallel computation capacities of FPGA, the rule is to design specific memory access architectures [17].…”

Section: A State Of the Artmentioning

confidence: 99%

Calibrating a predictive cache emulator for SoC design

Mancini

Pierrefeu

Larabi

et al. 2010

2010 NASA/ESA Conference on Adaptive Hardware and Systems

View full text Add to dashboard Cite

Pre-fetching in a memory hierarchy is known to alleviate the "memory wall" paradigm but its use is impeded because of the difficulty to estimate efficiency when used in a complex system such as a SoC (System on Chip) or NoC (Network on Chip). Therefore, some methods are needed to evaluate the benefit of pre-fetching at the earliest possible stage in a design flow to help the designer choose architectural parameters or transform the application algorithm.In this paper we show that the emulation platform implementing the nD-AP Cache (n-Dimensional Adaptive and Predictive Cache) allows to perform a platformindependent measurement of this cache efficiency. The nD-AP Cache performs pre-fetching in multidimensional arrays which are commonly used in image processing and multimedia applications. The obtained metric can be used to extrapolate the cache performance in a much broader system configuration. The method to compute this metric is the calibration process .The performed benchmarks show that the calibration process is confident. Also, we measured that the nD-AP Cache is two times faster than a standard PowerPC 2-way set associative cache in the context of an image processing kernel.

show abstract

Section: A State Of the Artmentioning

confidence: 99%

Calibrating a predictive cache emulator for SoC design

Mancini

Pierrefeu

Larabi

et al. 2010

2010 NASA/ESA Conference on Adaptive Hardware and Systems

View full text Add to dashboard Cite

show abstract

“…Cache architectures for general purpose processors have been optimized to deal with structured data and especially for multimedia applications [22], [8]. However, to exploit the parallel computation capacities of FPGA, the rule is to design specific memory access architectures [17].…”

Section: Related Workmentioning

confidence: 99%

Efficient Data Access Management for FPGA-Based Image Processing SoCs

Larabi

Mathieu

Mancini

2009

2009 IEEE/IFIP International Symposium on Rapid System Prototyping

View full text Add to dashboard Cite

In this paper, we propose a low-cost n-dimensional cache (nD-Cache) architecture for FPGA-Based image and signal processing Systems On Chip (SoCs). The architecture allows efficient access to structured data such as in 2D or 3D images. We developed a theoretical model for our architecture. It gives a methodology to define the cache's practical implementation based on the application and system parameters. Complexity and performance for selected image processing algorithms like jumping snake and 2D Back-Projection are measured and compared to classical solutions like associative caches. The architecture is shown to be efficient for tracking algorithm applications by exploiting spacial and temporal locality. Numerical results indicate that 50% improvement in run-time performance can be achieved.

show abstract

Object oriented prototyping at the system level: an image reconstruction application example

Mariatos

Birbas

et al.

Proceedings Seventh IEEE International Workshop on Rapid System Prototyping. Shortening the Path From Specification to Prototyp

View full text Add to dashboard Cite

A Novel System-on-Chip Architecture for Efficient Image Processing

Cited by 3 publications

References 4 publications

Calibrating a predictive cache emulator for SoC design

Calibrating a predictive cache emulator for SoC design

Efficient Data Access Management for FPGA-Based Image Processing SoCs

Object oriented prototyping at the system level: an image reconstruction application example

Contact Info

Product

Resources

About