Efficient Data Access Management for FPGA-Based Image Processing SoCs

Abstract

In this paper, we propose a low-cost n-dimensional cache (nD-Cache) architecture for FPGA-Based image and signal processing Systems On Chip (SoCs). The architecture allows efficient access to structured data such as in 2D or 3D images. We developed a theoretical model for our architecture. It gives a methodology to define the cache's practical implementation based on the application and system parameters. Complexity and performance for selected image processing algorithms like jumping snake and 2D Back-Projection are measured and compared to classical solutions like associative caches. The architecture is shown to be efficient for tracking algorithm applications by exploiting spacial and temporal locality. Numerical results indicate that 50% improvement in run-time performance can be achieved.

A platform for high level synthesis of memory-intensive image processing algorithms

“…In [11], traditional CPU caches were implemented on FPGAs, but these do not prefetch large memory blocks as required in image processing. The authors in [5] proposed a useful n-dimensional cache with active prefetching and our work integrates these concepts into a complete platform. The FlexWAFE project [4] also employed large external memories but could not comment on Xilinx SDRAM controller cores like MIG [9] and MPMC [10] that are currently available.…”

Calibrating a predictive cache emulator for SoC design

“…The nD-AP Cache aims at caching multidimensional data as described in [14]. Also it performs pre-fetching by estimating the future zones of data the processing unit is supposed to fetch.…”

“…The trackers try to estimate the zones of indexes the computing unit may fetch from an analysis of the past fetches and a prediction model. The nD-AP Cache architecture is modular and several kinds of trackers are available [14]. In the following, we consider a first order SC tracker which prediction model makes the hypothesis that the indexes of the fetch sequence evolves as a compound of a fast displacement around a low speed displacement.…”

“…In [14] we provided a model of performance of the nD-AP Cache. The efficiency is shown to depend on the characteristics of the fetch sequence and on the latency to the background memory mainly.…”

“…In previous works, we presented the nD-AP Cache concept [16], some examples of applications [10], a performance model [14] and a first method to automatically tune the prediction mechanism [15]. In this paper we show that an hardware emulation platform that implements the nD-AP Cache as a coprocessor can be used to evaluate the nD-AP Cache performance in a wider context:…”