A Novel System in Package with Fan-Out WLP for High Speed SERDES Application

Chen, Nan-Cheng; Hsieh, Tung-Hsien; Jinn, Jimmy; Chang, P.; Huang, Fandy; Xiao, Jw; Chou, Alan F.; Lin, Benson

doi:10.1109/ectc.2016.43

Cited by 47 publications

(1 citation statement)

References 1 publication

Supporting

Mentioning

Contrasting

Order By: Relevance

“…TSMC [29,30] presented two papers on FOWLP at ECTC2016: one is their integrated fan-out (InFO) wafer-level packaging for housing the most advanced AP for mobile applications [31], and the other is to compare the thermal and electrical performance between their InFO technology and the conventional fan-out flip chip-eWLB to make the RDLs for the chips to perform mostly lateral communications. During ECTC2016, ASE [35] and Mediatek [36] used a similar technology to fabricate the RDLs with FOWLP and showed that the TSV interposer, wafer bumping, fluxing, chip-to-wafer bonding, cleaning, and underfill dispensing and curing are eliminated, i.e., TSV-less interposers.…”

Section: Introductionmentioning

confidence: 99%

Recent Advances and Trends in Fan-Out Wafer/Panel-Level Packaging

Lau

2019

Journal of Electronic Packaging

View full text Add to dashboard Cite

The recent advances and trends in fan-out wafer/panel-level packaging (FOW/PLP) are presented in this study. Emphasis is placed on: (A) the package formations such as (a) chip first and die face-up, (b) chip first and die face-down, and (c) chip last or redistribution layer (RDL)-first; (B) the RDL fabrications such as (a) organic RDLs, (b) inorganic RDLs, (c) hybrid RDLs, and (d) laser direct imaging (LDI)/printed circuit board (PCB) Cu platting and etching RDLs; (C) warpage; (D) thermal performance; (E) the temporary wafer versus panel carriers; and (F) the reliability of packages on PCBs subjected to thermal cycling condition. Some opportunities for FOW/PLP will be presented.

show abstract

Section: Introductionmentioning

confidence: 99%