ground layout [ Fig. (7)] achieves a 15.5 dB gain at 5.2 GHz, similar to that predicted by the circuit simulation. Figure 9 shows the measured, circuit simulated and full-wave simulated noise figure of the LNA. The circuit simulation shows that the dual-band LNA achieves a 3 dB noise figure at both 2.4 and 5.2 GHz. The measured result shows that the noise figure is 4.2 dB at 2.4 GHz and is severely reduced to 6.8 dB at 5.2 GHz. The full-wave simulation shows that the noise figure, using the original ground layout for the LNA, is 5 dB at 5.2 GHz. This is 2 dB worse than the circuit simulation result at the same frequency. With the proposed ground layout, the noise figure is improved from 5 dB to 3.5 dB. This may be attributed to the improved gain as well as the reduced ground resistive element relating to the decreased length of the ground-return path.
CONCLUSIONIn this article, the ground layout effect, which significantly affects the gain performance of a CMOS concurrent dual-band LNA operating at 5.2 GHz, is analyzed using a full-wave simulation. As the circuit simulated and measured results show [(Figs. (5) and (9)], the layout effects do not substantially affect the performance of the RF integrated LNA at the 2.4 GHz frequency band. However, as the operating frequency increases to twice the 2.4 GHz frequency, the ground layout effects are no longer negligible, and there is significant deterioration in the performance of the LNA. Based on the analysis, we determine that the parasitic inductance produced by the ground-return path significantly reduces the gain of the LNA at the higher operating frequency band. By decreasing the area of the loop formed by the signal traces and the ground-return path and by placing the ground-return path close to the signal traces, the parasitic inductance is effectively reduced, thus achieving the improved performances of the LNA.