A novel strain enhanced CMOS architecture using selectively deposited high tensile and high compressive silicon nitride films

Abstract

A novel CMOS architecture utilizing tensilekompressive silicon nitride capping layers to induce tensilekompressive strain in NMOSFETPMOSFET channel regions was developed. NMOSFET device delivers 1.05mA/pm on-current for 7OnA/pm off-current at 1V drain voltage. PMOS device exhibits peak 66% increase of linear drain current and 55% increase of saturation current. It was shown that drain current improvements both for N-and PMOSFETs strongly correlate with channel doping levels. Therefore, advanced methods of shallow and low resistance junction formation are required for maintaining low channel doping concentration and efficiently utilizing channel strain at sub40nm gate length.

The Challenges of Advanced CMOS Process from 2D to 3D

“…This technique consists of a SiN x layer deposited around the gate stack as shown in Figure 4. By tuning the process parameters the stress amount and its type: tensile or compressive can be determined [34].…”

“…This technique consists of a SiNx layer deposited around the gate stack as shown in Figure 4. By tuning the process parameters the stress amount and its type: tensile or compressive can be determined [34]. The most effective method to induce stress in S/D is embedded SiGe (compressive stress for pMOS), Si:C (tensile stress for nMOS) or trench contact, and in metal gate [34].…”

“…By tuning the process parameters the stress amount and its type: tensile or compressive can be determined [34]. The most effective method to induce stress in S/D is embedded SiGe (compressive stress for pMOS), Si:C (tensile stress for nMOS) or trench contact, and in metal gate [34]. More aggressive scaled nodes have tighter contacted poly pitch (CPP), resulting in less room for gate and S/D.…”

Current status of CMOS low voltage and low power wireless IC designs

“…Depending on the material used and the growth conditions, one can achieve either uniaxial or biaxial stresses. Due to advantages related to n-channel threshold voltage shifts and p-channel mobility enhancements at low strain and high vertical electric fields [9][10][11], process induced uniaxial stresses are being adopted by the industry as the first generation of strained silicon devices.…”

Dimension Increase in Metal-Oxide-Semiconductor Memories and Transistors

“…Since an overlayer silicon has to be epitaxially deposited on Si-Ge layer, complicated fabrication processes are likely to delay the practical use of it. As a more practical structure, the usage of compressive and tensile chemical-vapor deposited (CVD) silicon-nitride films was proposed (Pidin et al, 2004), as shown (b) in Fig. 18 .…”