A novel self-aligned gate-overlapped LDD poly-Si TFT with high reliability and performance

Field Plate Optimization in Low-Power High-Gain Source-Gated Transistors

“…Several fabrication techniques [10][11][12][13] have been developed which improve the quality of the film in an attempt to ensure the same number of grain boundaries (or none) are present in the channel of every device and advanced device structures have been implemented in order to mitigate the kink effect. Device engineering techniques include: lightlydoped drain (LDD) [14][15]; gate-overlapping lightly-doped drain (GOLDD) [16] and drain field plate [17]. Their main role is to reduce the drain-field dependence of drain current, the main benefits being reduced power consumption in digital circuits [18] and improved signal amplification in analog blocks [19].…”

(Invited) Short Channel Effects and Drain Field Relief Architectures in Polysilicon TFTs

“…Mishima et al [25] also proposed a simplified method for forming self-aligned LDD regions by side etching of the Al-Nd layer in a AlNd/Mo terrace-structure gate electrode and using ion implantation at two different energies. However, while the Hatano et al [24] method is a high-temperature process, requiring the deposition of polysilicon for sidewall formation, the Mishima et al [25] approach provides poor control of the lateral extension of the LDD regions, relying upon the side etching rate of the Al-Nd layer. To solve these limitations, a process has been proposed by Glasse et al [9] in which conductive sidewall spacers were formed by n + aSi deposited by plasma enhanced CVD (PECVD), thus reducing the maximum processing temperature compared with the Hatano et al process.…”

“…GOLDD structures have been demonstrated to provide excellent drain field relief with reduced series resistance [23], however, the benefits of reducing channel length could be cancelled out by series resistance and overlap capacitance from disproportionately large field relief regions. Definition of submicron LDD regions is therefore essential, and several processes have been proposed [9,24,25]. Originally, Hatano et al [24] fabricated FSA-GOLDD devices by using doped polysilicon sidewall (defining LDD regions 180 nm in length) and showed the superior performance of FSA-GOLDD devices with respect to LDD or SA TFTs.…”

“…Definition of submicron LDD regions is therefore essential, and several processes have been proposed [9,24,25]. Originally, Hatano et al [24] fabricated FSA-GOLDD devices by using doped polysilicon sidewall (defining LDD regions 180 nm in length) and showed the superior performance of FSA-GOLDD devices with respect to LDD or SA TFTs. The process was inspired by the well-known technology of single crystal silicon MOSFETs, namely, the use of sidewall spacers acting as sub-micron and self-aligned masks for implant and etch processes.…”

“…Indeed, the LDD architecture has been shown to improve short channel effects [22] and electrical stability [20], although at the expenses of increased parasitic resistance [20]. Series resistance can be substantially reduced in the GOLDD structure [23], where the gate-drain overlap capacitance can be minimized by adopting a fully SA process using conductive sidewall spacers [9,24,25]. GOLDD structures have been demonstrated to provide excellent drain field relief with reduced series resistance [23], however, the benefits of reducing channel length could be cancelled out by series resistance and overlap capacitance from disproportionately large field relief regions.…”