A Novel Scan Segmentation Design for Power Controllability and Reduction in At-Speed Test

Zhou, Jiang; Xiang, Dong; Shen, Kele

doi:10.1109/ats.2015.9

Cited by 7 publications

(9 citation statements)

References 19 publications

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“…Scan architectures presented in [24], [25] split chains into multiple segments considering data dependency. During the capture operation, a selective number of segment groups are enabled in a cycle to capture the partial test response for each test pattern.…”

Section: Segmentation and Using Non-overlapping Or Staggered Clocksmentioning

confidence: 99%

“…After the clock frequency reaches shift speed, actual scan shifting starts. Segmentation techniques in [24], [25] involve cutting a functional clock into multiple branches to feed the individual segments. Unfortunately, cutting a clock creates clock divergence at the root of the functional clock tree.…”

Section: Segmentation and Using Non-overlapping Or Staggered Clocksmentioning

confidence: 99%

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Developments in scan shift power reduction: a survey

Sontakke,

Dickhoff

2023

Bulletin EEI

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While power reduction during testing is necessary for today's low-power devices, it also lowers test costs. Scan-based methods are the most widely used approach for testing integrated circuits (IC). Test vectors are shifted into and out of scan chains bit by bit during shift operation. The time required for shift operation dominates the test time. With the geometries shrinking (7 nm→5 nm→3 nm→1.8 nm), ICs are required to be tested for newer defects, increasing test time. The most effective way to reduce test time for scan operation is to increase the frequency of the shift operation. Reduction in shift power enables scan operation to be performed with increased frequency, reducing test time, and test cost. This paper presents a survey of techniques proposed recently for shift power reduction. Various techniques, including special flip-flop usage, segmentation, reordering, and low-pass filter, are being reviewed. The techniques are organized based on main attributes to underscore their similarities and differences. Pros and cons in terms of complexities involved in their implementation are discussed. We believe this paper will provide a point of reference for further studies in scan shift power reduction and will be helpful to both industry and academia.

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Section: Segmentation and Using Non-overlapping Or Staggered Clocksmentioning

confidence: 99%

Section: Segmentation and Using Non-overlapping Or Staggered Clocksmentioning

confidence: 99%

Developments in scan shift power reduction: a survey

Sontakke,

Dickhoff

2023

Bulletin EEI

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show abstract

“…Tables 3 to 5 present these categories. Launch-off capture (LOC) usage † [12], [17], [18], [20], [22]- [27], [28]- [31], [33] 3…”

Section: Classificationmentioning

confidence: 99%

“…Techniques using layout information † [12], [19], [20], [22], [25], [29], [38] † -Sections 4 and 5 do not have separate sub-sections for these techniques. They are covered as part of other sub-sections.…”

Section: Classificationmentioning

confidence: 99%

A survey of scan-capture power reduction techniques

Sontakke,

Dickhoff

2023

IJECE

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With the advent of sub-nanometer geometries, integrated circuits (ICs) are required to be checked for newer defects. While scan-based architectures help detect these defects using newer fault models, test data inflation happens, increasing test time and test cost. An automatic test pattern generator (ATPG) exercise’s multiple fault sites simultaneously to reduce test data which causes elevated switching activity during the capture cycle. The switching activity results in an IR drop exceeding the devices under test (DUT) specification. An increase in IR-drop leads to failure of the patterns and may cause good DUTs to fail the test. The problem is severe during at-speed scan testing, which uses a functional rated clock with a high frequency for the capture operation. Researchers have proposed several techniques to reduce capture power. They used various methods, including the reduction of switching activity. This paper reviews the recently proposed techniques. The principle, algorithm, and architecture used in them are discussed, along with key advantages and limitations. In addition, it provides a classification of the techniques based on the method used and its application. The goal is to present a survey of the techniques and prepare a platform for future development in capture power reduction during scan testing.

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“…To the simplest of our insight, this can be the first work to form move and catch management controllably with least fault coverage misfortune, very little check-information volume and no extra instrumentation overhead for at-speed progress fault test. Broad analyses are performed on reference circuit ISCAS89 and IWLS2005 to verify the viability of the projected strategy [7].…”

Section: Literatre Surveymentioning

confidence: 99%

Secure Fault Diagnosis for Framework on Chip Design and Testing

Swapna*,

Kamalahasan,

Mishra

et al. 2020

IJITEE

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Because of the extensive expense of semiconductor fabricating, most framework on-chip structure organizations redistribute their generation to seaward foundries. As a large portion of these gadgets are fabricated in situations of constrained trust that regularly need suitable oversight, various diverse dangers have risen. These incorporate unapproved overabundance of the ICs, offer of out-of-determination/rejected ICs disposed of by assembling tests, robbery of scholarly property, and figuring out of the structures. The Boolean calculations are effectively break keybased confusion techniques and therefore go around the essential destinations of metering and confusion. In this research paper, we present an innovation secure cell plan for executing the structure for-security foundation to avoid releasing the way to a foe under any conditions and produce fault free integrated circuit design. Our proposed structure is impervious to different known assaults at the expense of a next to no region overhead. This Proposed Framework Actualized utilizing Verilog HDL also recreated by Modelsim 6.4 c and Integrated by Xilinx device.

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A Novel Scan Segmentation Design for Power Controllability and Reduction in At-Speed Test

Cited by 7 publications

References 19 publications

Developments in scan shift power reduction: a survey

Developments in scan shift power reduction: a survey

A survey of scan-capture power reduction techniques

Secure Fault Diagnosis for Framework on Chip Design and Testing

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