A Novel Pattern Run-Length Coding Method for Test Data Compression

Wu, Diancheng; Liu, Yu; Zhu, Hongliang; Wang, Donghui; Chen, Hao

doi:10.1587/transele.e96.c.1201

Cited by 3 publications

(2 citation statements)

References 14 publications

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“…Here the main advantage being that test data compression can be done without requiring any structural information about the embedded cores, and can achieve a good compression ratio, without much trade-off in test power. A particular run-length coding method is explained in [9], wherein the compatibility of each pattern is analyzed and the codeword generated. In this paper, a similar concept is used, in which thecodeword is generated on the basis of the compatibility among the test patterns.…”

Section: +-Ieeementioning

confidence: 99%

Selective compression technique using Variable-to-Fixed coding

Jacob

Kumar

Manjurathi

2014

2014 International Conference on Communication and Signal Processing

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Inthis paper, we propose a code based technique, Variable-to-Fixed (V -F) coding, for power efficient test data compression. The proposed scheme with the aim of achieving high compression ratio and low power consumption relies on reducing, the number of bits for representing the original test vector and the number of transitions per second. Simulation results on ISCAS'89 benchmark circuits, demonstrate that this optimization methodology helps achieve reduced test data volume than previous schemes for cases where the number of specified bits in the test set is relatively few.

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Section: +-Ieeementioning

confidence: 99%

Selective compression technique using Variable-to-Fixed coding

Jacob

Kumar

Manjurathi

2014

2014 International Conference on Communication and Signal Processing

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“…The commonly used test vector compressed coding methods include pattern run-lenth (PRL) code [11,12], Huffman code [13], false discovery rate (FDR) code [14,15], nine-coded (9C) code [16], block merging (BM) code [12,17], and extended frequency-directed run-length (EFDR) code [18,19]. These methods can effectively achieve good compression effect and reduce the storage cost of test data.…”

Section: Introductionmentioning

confidence: 99%

Test Stimuli Segmentation and Coding Method

2018

Teh. vjesn.

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Test vector coding and data transmission are the key technologies in the design-for-test of digital integrated circuits (IC). Existing parallel input methods of test stimuli can reduce test application times; however, they need to occupy multiple input ports. Thus, a novel method of test stimuli coding and data transmission was proposed to reduce the test application time of the test vectors and reduce the number of input ports required for the parallel input of test stimuli. This method was based on the segmentation of test stimuli. First, the test stimuli were evenly segmented into eight-bit wide. Second, the eight-bit data of each segment were encoded to the five-bit data according to the compatibility between the test data of each segment. The eight-bit test stimuli input can be completed in one or two clock cycles of automatic test equipment (ATE) by using the five input ports of the chip. The corresponding decoding circuit was added inside the netlist of the circuit to realize the rapid input of the test stimuli. Lastly, the ISCAS'89 benchmark circuit was used to conduct experiments, results of this coding method were then compared with those of the serial input method. Results show that the encoding method proposed in this study can save an average of 37% of the parallel input data width and 81.7% of the test stimuli input time. The proposed method in this study can also reduce the test application time and the cost of the IC test. The findings of this study can provide guidance for improving the scan testing method of digital IC.

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