A Novel Parity Preserving Reversible Binary-to-BCD Code Converter with Testability of Building Blocks in Quantum Circuit

Misra, Neeraj Kumar; Sen, Bibhash; Wairya, Subodh; Bhoi, Bandan Kumar

doi:10.1007/978-981-10-8228-3_35

Cited by 4 publications

(2 citation statements)

References 12 publications

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“…In order to create this gate, 3 clock phases were used, and by using the proposed gate, a BCD to excess-3 code converter was presented. A BCD adder in reference [14] was presented. Te realization of this BCD adder involves the introduction of several innovative gates, namely, the half-adder/subtraction (HAS-PP), full-adder/subtraction (FAS-PP), and overfow-detection (OD-PP), all of which rely on paritypreserving logic synthesis.…”

Section: Literature Surveymentioning

confidence: 99%

Design of a Novel Decimal to Multicode Converter in QCA Technology

Fouladinia,

Gholami

2023

Journal of Electrical and Computer Engineering

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Researchers are always looking for the improvement of existing methods. Today, CMOS technology is widely used, which has some advantages and disadvantages. One of the alternative methods for CMOS technology is QCA technology which compared to CMOS, has the advantages of low energy consumption and small occupied area. In this paper, by using the concepts and methods of QCA technology, a digital code converter is presented. In this converter, a new gate is used, which can produce outputs such as 4-input AND, 4-input OR, 4-input NAND, and 4-input NOR. The proposed converter has 10 inputs and 12 outputs. The 10 inputs are decimal numbers from 0 to 9, producing the output equivalent to excess-3, BCD, and gray codes. One of the advantages of this circuit is providing three different codes per input in just one circuit. In addition, due to the use of the new 4-input gate, the occupied area and the number of used cells were minimized. Simulations were performed by using QCADesigner-E version 2.2, and outcomes illustrated that the occupied area is equal to 0.29 μm2 and 380 QCA cells with 7 clock phases are used. The energy dissipation of the presented circuit is 171 meV. Also, given the favorable performance exhibited by the 4-input gate across various measurement parameters, it possesses the capability to be efficiently employed within larger and intricately designed circuits.

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Section: Literature Surveymentioning

confidence: 99%

Design of a Novel Decimal to Multicode Converter in QCA Technology

Fouladinia,

Gholami

2023

Journal of Electrical and Computer Engineering

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“…However, as reversible circuits preserve every bit value from being lost, zero energy dissipation is allowed. Therefore, reversible logic introduces a promising solution to overcome the challenges in the design of high performance computing devices [1,2].…”

Section: Introductionmentioning

confidence: 99%

Reversible Logic Synthesis Using Binary Decision Diagrams With Exploiting Efficient Reordering Operators

2020

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With the continuous shrinkage of transistor sizes in very large scale integrated circuits, power consumption forms a serious concern to be tackled. With their ability to allow for zero energy dissipation, reversible circuits have been considered as promising solution to meetup with low power design requirements. Moreover, advances in their synthesis methodologies can be easily applied to quantum circuits due to the inherited reversibility of the latter. Although numerous algorithms have been proposed in the literature to synthesize reversible circuits and map them into their corresponding quantum circuits, the scalability and computational effort of such algorithms form a serious concern when synthesizing large size input functions. Binary Decision Diagram-based synthesis for reversible circuits has shown great evidence in realizing reversible circuits with low quantum cost through exploiting proper reduction rules for smaller graph size. However, the order of the variables in the decision diagram impacts its overall size, and thus, the cost of its corresponding reversible circuit. While several reordering algorithms have been proposed in this manner, their direct impact on the quantum cost has not been considered. In this paper, a Binary Decision Diagram-based algorithm for reversible circuit synthesis is proposed to synthesize reversible circuits for a given Boolean function with low quantum cost through exploiting a linearized relationship between the decision diagram size and the corresponding quantum cost. Thereafter, different decision diagram reordering algorithms have been integrated with the proposed algorithm and compared in terms of their impact on the quantum cost. Experimental results show that Genetic Algorithm-based reordering for decision diagram, supported with, cycle crossover, inverse mutation, and tournament selection, results in the least quantum cost of the output circuit if compared with other algorithms due to its property in preserving the nodes of the decision diagram in their near-optimal locations during the optimiation recipe.

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