A novel parallel prefix adder for optimized Radix-2 FFT processor

Thakur, Garima; Sohal, Harsh; Jain, Shruti

doi:10.1007/s11045-021-00772-1

Cited by 17 publications

(2 citation statements)

References 19 publications

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“…To achieve all of these goals, it is critical to develop an algorithm that solves all of these challenges. Although these methods are fast, the actual calculation time is determined by the processor’s system clock 1 . In processors, Multiplication is now an essential component of binary computers.…”

Section: Introductionmentioning

confidence: 99%

A modular technique of Booth encoding and Vedic multiplier for low-area and high-speed applications

Kalaiselvi,

Sabeenian

2023

Sci Rep

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A technique for efficiently multiplying two signed numbers using limited area and high speed is presented in this paper. This work uses both the Booth and Vedic multiplication sutra methodologies to enhance the speed and reduction in the area by using two VLSI architectures of radix encoding techniques—Radix-4 and Radix-8—with the Vedic multiplier. The functionality of the proposed methods is tested using an Artix-7 Field Programmable Gate Array (FPGA-XC7A100T-CSG324) in Xilinx Vivado 2019.1 and ASIC 45 nm technology. Two methods of Booth encoding using Vedic multiplier (Urdhva-Tiryakbhyam sutra) were used to develop, and examine the benefits of rapid computational multiplier. The results of the proposed multiplier for Booth-Vedic-Radix-4 encoding (BVR-4) decrease area by 89% and improve Area-Delay Product (ADP) by 72% for a 16-bit multiplier when subjected to other existing multipliers. The Booth-Vedic-Radix-8 (BVR-8) method shows that there will be an 89% reduction in area and an improvement in ADP by 72% for the 16-bit multiplier. The performance is evaluated regarding area occupancy (i.e., LUTs number) and propagation delay (output time). In terms of resource utilization, the proposed BVR-4 and BVR-8 multipliers outperform all the current designs with a marginal effect on speed and area for narrower bit-width ranges.

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Section: Introductionmentioning

confidence: 99%

A modular technique of Booth encoding and Vedic multiplier for low-area and high-speed applications

Kalaiselvi,

Sabeenian

2023

Sci Rep

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“…Compared to serial algorithms, CUDA-based parallel algorithms execute single instruction multithreaded commands, which can perform more operations and improve the efficiency of algorithm execution. However, due to the execution mode and memory access mode of the prefix sum algorithm [11][12][13], the execution process is prone to thread division and memory access conflict phenomena, which cannot effectively utilize the hardware resources of GPU. Prefix summation contains a large number of repetitive operations, which are simple but inefficient.…”

Section: Introductionmentioning

confidence: 99%

Parallel Differential Evolutionary Particle Filtering Algorithm Based on the CUDA Unfolding Cycle

Huang

Cao

2021

Wireless Communications and Mobile Computing

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Aiming at the problem of low statute efficiency of prefix sum execution during the execution of the parallel differential evolutionary particle filtering algorithm, a filtering algorithm based on the CUDA unfolding cyclic prefix sum is proposed to remove the thread differentiation and thread idleness existing in the parallel prefix sum by unfolding the cyclic method and unfolding the thread bundle method, optimize the cycle, and improve the prefix sum execution efficiency. By introducing the parallel strategy, the differential evolutionary particle filtering algorithm is implemented in parallel and executed on the GPU side using the improved prefix sum computation during the algorithm update. Through big data analysis, the results show that this parallel differential evolutionary particle filtering algorithm with the improved prefix sum statute can effectively improve differential evolutionary particle filtering for nonlinear system states and real-time performance in heterogeneous parallel processing systems.

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