A Novel No Miller Plateau SOI-LIGBT With Low Saturation Current and Improved Switching Performance

Zhang, Bingke; Kong, Moufu; Yi, Bo; Chen, Xingbi

doi:10.1109/ted.2020.2982656

Cited by 8 publications

(3 citation statements)

References 22 publications

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“…In the short-circuit condition, the most failures of devices are attributed to the activation of parasitic transistor, and adjusting hole current path is an efficiency way to suppress the latch up. The most effective approach to prevent the latch up is lowering the saturation current (Isat) through employing series diodes or MOSs to extract holes in drift region [15], [16], [17].…”

Section: Introductionmentioning

confidence: 99%

Four Hybrid Gates SOI Lateral Insulated Gate Bipolar Transistor With Improved Carrier Controllability

Pan

et al. 2023

IEEE J. Electron Devices Soc.

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Easy inter-connection is a crucial advantage of the single-chip power ICs, which makes power devices with multiple ports easy to improve carrier controllability without increasing process difficulty. Electrical characteristics of the power devices get further improved thanks to the advanced carrier controllability. In this paper, a silicon-on-isolator lateral IGBT (SOI-LIGBT) featured four hybrid gates is proposed to obtain outstanding carrier controllability in turn-on, turn-off and short-circuit conditions for the first time. Four hybrid gates include three planar gates (G 1 , G 2 and G 3 ) and a trench gate (G 4 ), of which G 3 and G 4 are grounded gate to lower saturation current and suppress latch up. Low turn-off time (t OFF ), di/dt and improved short-circuit withstanding capability are obtained through providing different input signals to these gates. In the turn-on, G 2 is pre-charged to a stable voltage equal to gate voltage (V G1 ) to suppress the high di/dt before V G1 starts to rise. In the turn-off, a P-type inversion is induced by the negative voltage of G 2 (V G2 ), which provides a low-resistance hole current path to extract the stored holes. In the short-circuit condition, G 3 and G 4 are both shorted to the ground to lower the saturation current and suppress the activation of parasitic NPN transistor, resulting in an improved short-circuit withstanding time (t SC ). Compared with the conventional SOI-LIGBT, t OFF and di/dt are reduced by 43.6% and 53.08%, and t SC is prolonged from 3.04µs to 8.89µs at DC bus voltage of 400V.INDEX TERMS Hybrid gates, carrier controllability, turn-on, di/dt, turn-off time, short-circuit, short-circuit withstanding time, SOI, lateral IGBT, LIGBT, SOI-LIGBT.

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Section: Introductionmentioning

confidence: 99%

Four Hybrid Gates SOI Lateral Insulated Gate Bipolar Transistor With Improved Carrier Controllability

Pan

et al. 2023

IEEE J. Electron Devices Soc.

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“…Compared with currently used vertical design for IGBT, lateral design with flip-chip technique can lower the cost of the assembly while enable advanced embedding and stacking [7]. Moreover, the SOI LIGBTs can achieve significantly lower leakage currents and better dielectric-isolation (DI) capability, which reduce power consumption during normal operation [8,9,10,11,12].…”

Section: Introductionmentioning

confidence: 99%

Novel low loss and snapback-free SOI LIGBT controlled by anode junction self-built potential

Wang

Sun

Duan

et al. 2022

IEICE Electron. Express

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In this work, we evaluated a novel low loss and snapbackfree silicon-on-insulator lateral insulated gate bipolar transistor (SOI LIGBT) by numerical simulation, which utilizes the inherent junction self-built potential (JSBP) to form depletion region at the anode. When the anode voltage (VAC) is less than built-in potential (Vbi), the introduced electron flowing channel between P-anode pillars is occupied by the depletion region, which hinders electron current from flowing into N-anode and limits the device to working in MOS mode. Furthermore, due to the offset effect for the JSBP by higher VAC, the depletion region disappears and the anode PN junction turns on, which makes the device work in IGBT mode forming normal electron and hole current. At the same forward voltage drop (VF) of 1.64V, extra electron flowing channel makes the turn-off loss (Eoff) of proposed JSBP LIGBT 22.1% lower than that of conventional (Conv.) LIGBT. Moreover, considering to the same Eoff of 0.3mJ/cm 2 , the depletion region with low VAC contributes to relatively enhanced conductivity modulation, which makes VF of proposed JSBP LIGBT reduce by 19.6% compared to separated shorted-anode (SSA) LIGBT, while also completely eliminates snapback effect. Therefore, the proposed JSBP LIGBT gains the best trade-off performance between VF and Eoff.

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“…Lateral insulated gate bipolar transistor (LIGBT) is a popular power device due to its voltage control and low power loss at forward conduction, which is widely used in the field of the power integrated circuits. [1][2][3][4][5][6][7][8][9] However, the excessive carriers in the N-drift lead to the large turn-off loss E off . [10][11][12][13][14][15][16][17] The shorted anode (SA) LIGBT can effectively accelerate the extraction of electrons by introducing the N+ anode in anode.…”

Section: Introductionmentioning

confidence: 99%

Snapback-free shorted anode LIGBT with controlled anode barrier and resistance*

Li¹,

Zhang²,

Chen³

et al. 2021

Chinese Phys. B

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A novel shorted anode lateral-insulated gate bipolar transistor (SA LIGBT) with snapback-free characteristic is proposed and investigated. The device features a controlled barrier V barrier and resistance R SA in anode, named CBR LIGBT. The electron barrier is formed by the P-float/N-buffer junction, while the anode resistance includes the polysilicon layer and N-float. At forward conduction stage, the V barrier and R SA can be increased by adjusting the doping of the P-float and polysilicon layer, respectively, which can suppress the unipolar mode to eliminate the snapback. At turn-off stage, the low-resistance extraction path (N-buffer/P-float/polysilicon layer/N-float) can quickly extract the electrons in the N-drift, which can effectively accelerate the turn-off speed of the device. The simulation results show that at the same V on of 1.3 V, the E off of the CBR LIGBT is reduced by 85%, 73%, and 59.6% compared with the SSA LIGBT, conventional LIGBT, and TSA LIGBT, respectively. Additionally, at the same E off of 1.5 mJ/cm2, the CBR LIGBT achieves the lowest V on of 1.1 V compared with the other LIGBTs.

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A Novel No Miller Plateau SOI-LIGBT With Low Saturation Current and Improved Switching Performance

Cited by 8 publications

References 22 publications

Four Hybrid Gates SOI Lateral Insulated Gate Bipolar Transistor With Improved Carrier Controllability

Four Hybrid Gates SOI Lateral Insulated Gate Bipolar Transistor With Improved Carrier Controllability

Novel low loss and snapback-free SOI LIGBT controlled by anode junction self-built potential

Snapback-free shorted anode LIGBT with controlled anode barrier and resistance*

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