A Novel Negative Capacitance FinFET With Ferroelectric Spacer: Proposal and Investigation

Chauhan, Vibhuti; Samajdar, Dip Prakash; Bagga, Navjeet; Dixit, Ankit

doi:10.1109/tuffc.2021.3098045

Cited by 21 publications

(16 citation statements)

References 12 publications

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“…The reduction in the same is due to degradation in mobility of charge carriers at high gate bias [36]. The values obtained for I on /I off , g m , f T , TFP, g m /I ds , R out , intrinsic delay, and f max are in unison and better than [17,18,20,31,33,36]. Therefore, the proposed device shows the optimal RF/Analog performance at FE thickness of 20 nm.…”

Section: Effect Of T Fe On DC and Rf/analog Performancementioning

confidence: 77%

“…It is clear from the figure that, in saturation region with the increase in drain voltage the output current decreases showing negative differential resistance region (NDR). The same is due to increased drain electric field lines that started affecting the FE polarization at higher V ds [33]. The transconductance (g m ), which is the rate of change of I ds with applied V gs at constant drain voltage, signifies the device gain performance.…”

Section: Effect Of T Fe On DC and Rf/analog Performancementioning

confidence: 99%

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Performance optimization of high-K GAA-PZT negative capacitance FET MFIS silicon nanowire for low power RFIC and analog applications

Kumar,

Maurya,

Malvika

et al. 2023

Phys. Scr.

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In this article, Gate-All-Around Lead Zirconate Titanate Negative Capacitance (GAA PZT- NCFET) based Silicon Nanowire (SiNW) device architecture is investigated for the RF/Analog applications using Sentauras TCAD simulations. In this study the variation of ferroelectric layer thicknesses (tfe) have been systematically investigated. The proposed device yields higher values of on current, transconductance,cut off frequency, TFP, and Ion/Ioff ratio and lower values of off current, SS and threshold voltage, compared to baseline device. The proposed device delivers Ion, gm, fT, and TFP as 3.38 mA, 9.6 mS, 7.625 THz, and 74.85 THz/V, respectively which are 220 %, 219%, 95% and 259% respectively, higher than the baseline device. Moreover, the Ion/Ioff ratio for the proposed work is 8×1013 which is 7.1×103 times that of baseline device showing a monumental increment in this ratio. Furthermore, the effect of FE thicknesses on various linearity parameters, higher order harmonics, voltage intercept points (VIP2, VIP3), third order power intercept (IIP3) and third order intermodulation distortion (IMD3) have been investigated thoroughly. The proposed device structure offers lower values of higher order harmonics and higher values of voltage intercept points. Also, the IIP3 and IMD3 have been improved. Therefore, the linearity parameters of the device have been significantly improved when compared to the baseline device. The alluring results have been utilized to optimize the bias point of the presented device. Owing to , thethe improved RF/Analog and linearity performance presented device could be utilized for imminent next generation low power RFIC applications.

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Section: Effect Of T Fe On DC and Rf/analog Performancementioning

confidence: 77%

Section: Effect Of T Fe On DC and Rf/analog Performancementioning

confidence: 99%

Performance optimization of high-K GAA-PZT negative capacitance FET MFIS silicon nanowire for low power RFIC and analog applications

Kumar,

Maurya,

Malvika

et al. 2023

Phys. Scr.

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“…Finally, in figure 1(b), the improvement in the device performance is presented, which is obtained for the NC-FinFET at different drain biases. The details of the calibration procedure are discussed in [11,13].…”

Section: Tcad Validation Proceduresmentioning

confidence: 99%

“…Several studies have been conducted to date to increase the performance of NC-based FETs and FinFETs, respectively. The incorporation of device engineering approaches, such as work function variability [8,9], material-structure evaluation [8,9], and spacer engineering [10][11][12][13], among others, has been published in recent years. However, the use of such variable permittivity spacers lowers the carrier mobility through the trap formation caused by Coulombic scattering [14] and affects circuit delays due to the increased fringe capacitance [15].…”

Section: Introductionmentioning

confidence: 99%

Buried interfacial gate oxide for tri-gate negative-capacitance fin field-effect transistors: approach and investigation

Chauhan

Samajdar

2023

J. Phys. D: Appl. Phys.

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Negative Capacitance Fin field-effect transistor (NC-FinFET), due to its superior gate electrostatics and dominance over the short channel effects (SCEs), has been the key technology over the conventional devices. However, the improved device performance in terms of the various engineering practices, have paved the pathway for the advancement of NC-FinFETs. In the following work, we have proposed a novel buried oxide strategy for the NC-FinFET architecture, in which we have altered the depth of the Interfacial gate oxide (IGO) layer inside the channel and analyzed the performance characteristics using TCAD Sentaurus. Initially, we have varied the IGO thickness that is going to be buried inside the channel and performed a comparative analysis between the DC, mixed-mode and SCE parameters for the various buried configurations of the proposed NC-FinFET, in order to realize the optimized depth. We have also presented the tolerable degradation in the circuit characteristics that occurs with the varying BIGO depth. Lastly, it can be inferred from the presented interface trap discussion that the idea of buried IGO thickness holds well for the low-power electronics.

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“…To counteract this impact and ensure the continuation of Moore's law in semiconductor devices, much research has been conducted on innovative device physics and structure with the goal of lowering the operating voltage of the device. [1][2][3][4][5] Although III-V materials such as GaAs, InGaAs, InP, GaAsSb, and InGaSb have gained increasing popularity among material physicists and device engineers in recent years, these materials are particularly attractive to these groups because of their wide range of applications in the area of optical and electrical devices. [6][7][8][9][10] III-V compounds such as BGaAs are extensively used for different applications such as photodetectors, solar cells, and quantum dots due to its tunable direct band gap.…”

Section: Introductionmentioning

confidence: 99%

Impact of the mole fraction modulation on the RF/DC performance of GaAs_1−xSb_x FinFET

Dixit

Samajdar

Bagga

2021

Int J Numerical Modelling

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The impact of mole fraction variation on the RF/DC performance of GaAs 1Àx Sb x -based FinFET has been examined in this study. Changing the Sb mole fraction has substantial effect on the electronic band parameters of GaAs, which directly affects the device performance. Electrical properties of the device including electron density and mobility fluctuation are investigated as a function of Sb mole fraction. Additionally, device DC performance parameters such as the I ON /I OFF ratio, threshold voltage, transconductance, and device node capacitance, such as C gg and C ds , are studied using a technology computer-aided design (TCAD) simulator. The mole fraction dependence of the gate capacitance dictates the application of the proposed FinFET in the RF and high-frequency domains. A detailed investigation of the figures of merits such as intrinsic gain, intrinsic delay, dynamic power dissipation, power delay product, energy dissipation, and unity gain bandwidth reveals that GaAsSb can be a potential material for realization of low-power analog and digital circuits. The proper tuning of the mole fraction can help to optimize the device performance.

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A Novel Negative Capacitance FinFET With Ferroelectric Spacer: Proposal and Investigation

Cited by 21 publications

References 12 publications

Performance optimization of high-K GAA-PZT negative capacitance FET MFIS silicon nanowire for low power RFIC and analog applications

Performance optimization of high-K GAA-PZT negative capacitance FET MFIS silicon nanowire for low power RFIC and analog applications

Buried interfacial gate oxide for tri-gate negative-capacitance fin field-effect transistors: approach and investigation

Impact of the mole fraction modulation on the RF/DC performance of GaAs_1−xSb_x FinFET

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A Novel Negative Capacitance FinFET With Ferroelectric Spacer: Proposal and Investigation

Cited by 21 publications

References 12 publications

Performance optimization of high-K GAA-PZT negative capacitance FET MFIS silicon nanowire for low power RFIC and analog applications

Performance optimization of high-K GAA-PZT negative capacitance FET MFIS silicon nanowire for low power RFIC and analog applications

Buried interfacial gate oxide for tri-gate negative-capacitance fin field-effect transistors: approach and investigation

Impact of the mole fraction modulation on the RF/DC performance of GaAs1−xSbx FinFET

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Impact of the mole fraction modulation on the RF/DC performance of GaAs_1−xSb_x FinFET