Performance optimization of high-K GAA-PZT negative capacitance FET MFIS silicon nanowire for low power RFIC and analog applications

Abstract

In this article, Gate-All-Around Lead Zirconate Titanate Negative Capacitance (GAA PZT- NCFET) based Silicon Nanowire (SiNW) device architecture is investigated for the RF/Analog applications using Sentauras TCAD simulations. In this study the variation of ferroelectric layer thicknesses (tfe) have been systematically investigated. The proposed device yields higher values of on current, transconductance,cut off frequency, TFP, and Ion/Ioff ratio and lower values of off current, SS and threshold voltage, compared to baseline device. The proposed device delivers Ion, gm, fT, and TFP as 3.38 mA, 9.6 mS, 7.625 THz, and 74.85 THz/V, respectively which are 220 %, 219%, 95% and 259% respectively, higher than the baseline device. Moreover, the Ion/Ioff ratio for the proposed work is 8×1013 which is 7.1×103 times that of baseline device showing a monumental increment in this ratio. Furthermore, the effect of FE thicknesses on various linearity parameters, higher order harmonics, voltage intercept points (VIP2, VIP3), third order power intercept (IIP3) and third order intermodulation distortion (IMD3) have been investigated thoroughly. The proposed device structure offers lower values of higher order harmonics and higher values of voltage intercept points. Also, the IIP3 and IMD3 have been improved. Therefore, the linearity parameters of the device have been significantly improved when compared to the baseline device. The alluring results have been utilized to optimize the bias point of the presented device. Owing to , thethe improved RF/Analog and linearity performance presented device could be utilized for imminent next generation low power RFIC applications.

Design and performance analysis of Si-SiGe heterostructure based double gate feedback FET

“…This occurs because semiconductor carriers obey the Boltzman statics [5]. Numerous studies, including those on the tunneling field-effect transistor (TFET) [6][7][8], impact-ionization MOSFET (i-MOSFET) [9,10], ferroelectric negative-capacitance field-effect transistor (NCFET) [11,12], nano-electro-mechanical field-effect transistor (NEMFET) [13], and feedback field-effect transistor (FBFET) [14][15][16] have offered methods to overcome the SS limitations of MOSFETs.…”

Design and performance analysis of tri-layered strained Si/Si1–x Ge x /Si heterostructure DG feedback FET

“…As a result, it has not been possible to scale down the power-supply voltage (V DD ) in silicon-based transistors in accordance with the physical scaling of the transistor dimension. Numerous studies [6][7][8][9][10][11][12][13] have proposed remedies to the aforementioned issues. Some of them altered the hitherto typical MOS architectures, while others subtly utilized new device operation principles.…”

“…Some of them altered the hitherto typical MOS architectures, while others subtly utilized new device operation principles. Tunnel field-effect transistors (TFET) [6][7][8], ferroelectric negative-capacitance field-effect transistors (NC-FET) [9,10], impact-ionization MOSFETs (i-MOS) [11,12], and nano electro-mechanical field-effect transistors (NEMFET) [13] are some of the devices that have previously been proposed to overcome the Boltzman limitations of MOSFETs.…”