A novel low voltage and high speed CMOS charge pump circuit

Fan, Qing; Xiansong, Fu; Niu, Pingjuan; Yang, Guanghua; Gao, Tiecheng

doi:10.1109/icsps.2010.5555828

Cited by 4 publications

(2 citation statements)

References 7 publications

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“…According to the results in table 2, the proposed PLL performs better than the conventional one in terms of power. In order to compare performance, PLLs with various charge pumps [32][33][34][35] are simulated and shown in this table 4. The power waveform of the proposed PLL is depicted in figure 12 and the phase noise variation of Conventional and Proposed Charge Pumps is shown in figure 13.…”

Section: Resultsmentioning

confidence: 99%

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Self-cascode and self-biased Dickson charge pump for fast locking wide lock range PLL with reduced phase noise

Buddha,

Jena,

Pandey

et al. 2024

Eng. Res. Express

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The charge pump is a fundamental component in phase-locked loop (PLL) circuits, essential for generating a control voltage that adjusts the frequency and phase of the voltage-controlled oscillator (VCO) to match the input reference signal. The self-cascode and self-biased Dickson charge pump architecture presented in this work addresses several key challenges encountered in conventional PLL designs. By integrating self-cascode techniques, the charge pump exhibits enhanced chargingand discharging capabilities, enabling faster locking times essential for wide lock range PLLs. This comprehensive approach offers a compact and integrated solution that simultaneously enhances locking speed, widens the lock range, reduces phase noise, and simplifies design complexity, making it highly suitable for demanding applications in communication systems, radar, and wireless technologies. The novel CP is implemented in 90 nm CMOS technology with a 1.0-V supply voltage. It is integrated with a phase-locked loop (PLL) that has a lock time of 1.0us, a negligible reference spur, and an average power consumption of 34.7 mW. The PLL is having a wide lock range of 0.98 GHz to 2.98 GHz with a center frequency of 1.54 GHz where the phase noise is calculated to be -100.9 dBc/Hz at 1 MHz offset frequency. This makes the PLL compatible with both GSM having 1.8 GHz and Wi-Fi having 2.8 GHz frequency bands. The proposed PLL is also capable of operating at a wide range of temperatures (27°C,0 °C,27 °C,84 °C) and at various corners (NN, FS, SF, SS,FF) making it reliable in adverse circumstances.

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Section: Resultsmentioning

confidence: 99%

“…It uses a single, two-stage amplifier for current steering and mismatch reduction. The study [15] designs a unique low-voltage, high-speed CMOS charge pump circuit for PLL. The novel structure, which uses an N well mixed-signal Chartered 0.35 m CMOS technology and is simulated using Hspice, avoids the frequent spurious jump phenomena.…”

Section: Introductionmentioning

confidence: 99%