A novel low specific on-resistance double-gate LDMOS with multiple buried p-layers in the drift region based on the Silicon-On-Insulator substrate

Chen, Yinhui; Hu, Shengdong; Cheng, Kun; Jiang, Yuyu; Luo, Jie; Wang, Jianan; Tang, Fang; Zhou, Xichuan; Zhou, Jianlin; Gan, Ping

doi:10.1016/j.spmi.2015.09.037

Cited by 13 publications

(7 citation statements)

References 19 publications

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“…Table 2 lists the BV, R on,sp , FOM1, Q g (gate charges, V gs from 0 V to 15 V), Q gd (gate-drain charges) and FOM2 (Q gd × R on,sp ) of this work and others. Compared with [10,15,17], it is notable that SLTGN-LDMOS has a minimum R on,sp of 1.46 mΩ•cm 2 and a maximum FOM1 of 18.13 MW•cm −2 . Although the SLTGN-LDMOS cannot withstand higher voltages compared to other devices, it has already achieved a very high BV because its lateral size is only 4.5 μm.…”

Section: Simulation Results and Discussionmentioning

confidence: 99%

“…Different from the previous uniformly doped NPN triple structure, [13] introduced a novel partial linear variable doping n-type top layer to further optimize the performance. References [14][15][16] utilized dual trench gate (DTG) to form more electron accumulation layers and current conduction paths near the P-well, greatly reducing R on,sp without sacrificing BV. However, a single DTG has no noticeable effect on enhancing BV.…”

Section: Introductionmentioning

confidence: 99%

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Study of ultra-low specific on-resistance and high breakdown voltage SOI LDMOS based on electron accumulation effect

Lyu,

Dai,

Wang

et al. 2023

Eng. Res. Express

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A novel stepped L-shaped trench gate silicon-on-insulator (SOI) lateral double-diffused metal oxide semiconductor field-effect transistor (LDMOS) with N-pillar (SLTGN-LDMOS) is proposed. SLTGN-LDMOS contains a highly doped N-pillar, assisting in reducing the specific on-resistance (Ron,sp). The stepped L-shaped trench gate (SLTG) attracts electrons to attach to the edge of the trench, thus directing more current to flow along the edge, which decreases Ron,sp effectively. Furthermore, new electric field peaks are generated on the surface of the drift region, thus increasing the breakdown voltage (BV). As a result, compared with the conventional structure (C-LDMOS), the BV of SLTGN-LDMOS increases from 63 V to 162.7 V, and the Ron,sp decreases from 1.85 mΩ·cm2 to 1.46 mΩ·cm2. Then, the figure of merit (FOM1, BV2 / Ron.sp) increases remarkably from 2.15 MW/cm2 to 18.13 MW/cm2. In addition, the maximum surface temperature of SLTGN-LDMOS is 395.3 K, slightly lower than the 398.7 K of C-LDMOS.

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Section: Simulation Results and Discussionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Study of ultra-low specific on-resistance and high breakdown voltage SOI LDMOS based on electron accumulation effect

Lyu,

Dai,

Wang

et al. 2023

Eng. Res. Express

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“…The ON resistance is calculated as the ratio of V ds and I ds from the linear region of the output characteristic curve for both the devices [18,19]. Being the major contribution of ON resistance in the trench MOSFET, the drift region resistance and thus the total resistance in the proposed SBGPMOS is reduced by a high drift doping concentration of 5×10 15 cm −3 in the proposed structure as compared to 5.6×10 14 cm −3 in the conventional one.…”

Section: Simulation Results and Discussionmentioning

confidence: 99%

High performance selective buried double gate power MOSFET

Nigar

Loan

Alharbi

2019

Semicond. Sci. Technol.

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In this letter, we propose a dual laterally aligned poly-silicon selective buried gates power MOSFET (SBGP-MOSFET). The proposed structure significantly improves the ON resistance (R on )-breakdown voltage tradeoff, reduces gate-drain capacitance (C GD ) and eliminates the formation of parasitic n-p-n transistor in comparison to the conventional vertical trench power MOSFET. The two buried gates provide a large separation between the gate and drain thus reduces the gate-drain coupling, gate-drain capacitance (C gd ) and switching losses. A two dimensional simulation study shows that the proposed SBGP-MOSFET achieves a significant reduction in ON resistance, 48.33% reduction in Q gd and ∼13% increase in the breakdown voltage in comparison to the conventional device.

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“…limit' relationship of R on,sp ∝ BV 2.5 , which leads to high power consumption, many methods have been proposed to improve the trade-off relationship between the R on,sp and BV [4][5][6][7][8][9][10][11][12][13][14][15][16][17][18][19][20][21]. By introducing a P-type region into the N-drift, typical RESURF [6][7][8][9][10][11][12][13] and superjunction [14][15][16][17][18][19][20][21] technologies not only decrease the R on,sp by enhancing the depletion effect to increase the N-drift doping concentration (N d ), but also increase the BV by modulating the electric field distribution. However, the R on,sp of these methods is strongly dependent upon the N d , and charge imbalance will result in BV degradation.…”

Section: Introductionmentioning

confidence: 99%

Simulation and experimental study on a high figure of merit LDMOS with ingenious layout design

Wei¹,

Dai²,

Ma³

et al. 2022

Semicond. Sci. Technol.

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To improve the tradeoff relationship between the specific on-resistance (Ron,sp) and breakdown voltage (BV), a novel lateral double-diffusion metal-oxide-semiconductor field effect transistor (LDMOSFET) with ingenious layout design is proposed and investigated by simulations and experiments. The proposed LDMOS features a specific convex-shape field plate (CFP) structure at source side and two separated integrated diodes (SID) at the drain side. On one hand, a continuous electron accumulation layer is formed from source to drain in the on-state, providing an ultralow current path to decrease the specific on-resistance (Ron,sp). On the other hand, the CFP and SID structures allow the proposed device to make full use of the drift length to sustain the off-state voltage, so that the novel device could maintain the same BV level with a shorten drift length. Thus, the proposed CFP-SID LDMOS achieves a much lower Ron,sp and better Ron,sp-BV tradeoff relationship. The experimental results illustrate that the CFP-SID LDMOS realizes a BV of 518V and Ron,sp of 23.5 mΩ·cm2 with a high figure of merit (FOM) of 11.42MW/cm2. Compared with the triple-RESURF LDMOS under the same BV, the proposed device decreases the Ron,sp by 53.8%.

show abstract

A novel low specific on-resistance double-gate LDMOS with multiple buried p-layers in the drift region based on the Silicon-On-Insulator substrate

Cited by 13 publications

References 19 publications

Study of ultra-low specific on-resistance and high breakdown voltage SOI LDMOS based on electron accumulation effect

Study of ultra-low specific on-resistance and high breakdown voltage SOI LDMOS based on electron accumulation effect

High performance selective buried double gate power MOSFET

Simulation and experimental study on a high figure of merit LDMOS with ingenious layout design

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