A novel low power multiplexer-based full adder cell

Alhalabi, Bassem; Al-Sheraidah, A.

doi:10.1109/icecs.2001.957484

Cited by 10 publications

(5 citation statements)

References 7 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…They were named: cmos_26 [3], cmos_28 [3], cpl [5], sr_cpl [7], dcvs [4], bay_10a [13], bay_10b [14], bay_14a [9], bay_14b [10], bay_16 [12], full_rest [15], mux_based [16], tran_funct [8], wey_chow [17], wu_ng [11], our first proposal ( Figure 3) using XOR/XNOR gates designed with logic style DPL (Ours_1), and a second proposal ( Figure 4) using XOR/XNOR gates designed with logic style SR-CPL (Ours_2).…”

Section: Simulation Resultsmentioning

confidence: 99%

See 1 more Smart Citation

An alternative logic approach to implement high-speed low-power full adder cells

Aguirre¹,

Linares²

2005

Proceedings of the 18th Annual Symposium on Integrated Circuits and System Design - SBCCI '05

View full text Add to dashboard Cite

This paper presents a high-speed low-power 1-bit full adder cell designed upon an alternative logic structure to derive the SUM and CARRY outputs. Hspice and Nanosim simulations show that this full adder cell designed using a 0.35µm CMOS technology and supplied with 3.3V, exhibits delay and power dissipation around 720ps and 840µW, respectively. These features reflect an overall improvement of 30% in the power-delay metric, when compared with the performance of other realizations recently published as well featured cells for low-power applications.

show abstract

Section: Simulation Resultsmentioning

confidence: 99%

“…Chronologically, some of them are: 14TA [9], 14TB [10], wu_ng [11], 16T [12], 10TA [13], 10TB [14], full_rest [15], mux_based [16], and wey_chow [17].…”

Section: B a So Comentioning

confidence: 99%

An alternative logic approach to implement high-speed low-power full adder cells

Aguirre¹,

Linares²

2005

Proceedings of the 18th Annual Symposium on Integrated Circuits and System Design - SBCCI '05

View full text Add to dashboard Cite

show abstract

“…[7] has their design on the full adder to be more area efficient and low powered which uses Multiplexers into the design. [8] showcases their take on the full adder design that uses six multiplexer gates, which will be then replaced with two transistor Multiplexers that gives the MBA-T12 cell. Finally, [9] also proposed another full adder design that also uses six Multiplexers gates with all of the internal gate nodes directly inputed with fresh signal for faster transitions to output signals.…”

Section: Literature Reviewmentioning

confidence: 99%

Design and Analysis of Full Adder Using 0.6 Micron CMOS Technology

Fei¹,

Rahman²,

Subramaniam³

et al. 2023

Malaysian J. Sci. Adv. Tech.

View full text Add to dashboard Cite

The design of a full adder involves the use of logic gates so that the design can convert 8 inputs to create a byte-wide adder and to force the carry bit to the other adder. However, the uses of multiplexers to replace the logic gates in the construction of the full adder is proven to be possible due to the function of the multiplexers to act as the digital switch in the system that provides the flow of digital information from multiple inputs into an output. This research aims to explore the possibility of implementing the multiplexers into the design of the full adder and to analyse the different possible full adder design using the multiplexers. Using the multiplexers also allows for fewer logic gates to be used in the design of the full adder, which reduces the overall area coverage of the full adder. However, adding multiplexers does not make a complete adder more efficient and may slow it down. Thus, this article compares a conventional full adder with logic gates, a full adder with two 2:1 multiplexers, and a full adder with six 2:1 multiplexers in terms of power usage, time delay of the Sum and Carry outputs, and technology (0.6 μm).

show abstract

“…Multiplexer based full adder cell was proposed by Alhalabi, B. and Al-Sheraidah [1] in 2001 that uses 23 % less power and was 64 % faster. The use of multiplexer not only reduces the transition activity and charging recycling capability, but also make entire signal gates directly excited by the fresh input signals leading to noticeable reduction in short-current power consumption.…”

Section: Previous Workmentioning

confidence: 99%

Energy efficient and high performance 64-bit Arithmetic Logic Unit using 28nm technology

Murgai

Gupta

Muthukrishnan

2015

2015 International Conference on Advances in Computing, Communications and Informatics (ICACCI)

View full text Add to dashboard Cite

Arithmetic Logic Units are one of the vital unit in general purpose processors and major source of power dissipation. In this paper we have demonstrated an optimized Arithmetic and Logic Unit through the use of an optimized carry select adder. Carry select adders have been considered as the best in their category in terms of power and delay. In this context a full adder optimized in terms of power has been used in synthesizing a carry select adder. Combined with the new adder structure, there is a substantial improvement in terms of power and delay. The total device power and hierarchy power has been reduced to 12.5 % and 53.39 % respectively. 3 % reduction in total completion time has also been observed. The circuit has been synthesized on kintex FPGA through Xilinx 14.3 using 28 nm technology in Verilog HDL and results has been simulated on Modelsim 10.3c. The design is verified using System Verilog on QuestaSim in UVM environment.

show abstract

A novel low power multiplexer-based full adder cell

Cited by 10 publications

References 7 publications

An alternative logic approach to implement high-speed low-power full adder cells

An alternative logic approach to implement high-speed low-power full adder cells

Design and Analysis of Full Adder Using 0.6 Micron CMOS Technology

Energy efficient and high performance 64-bit Arithmetic Logic Unit using 28nm technology

Contact Info

Product

Resources

About