An alternative logic approach to implement high-speed low-power full adder cells

Abstract

This paper presents a high-speed low-power 1-bit full adder cell designed upon an alternative logic structure to derive the SUM and CARRY outputs. Hspice and Nanosim simulations show that this full adder cell designed using a 0.35µm CMOS technology and supplied with 3.3V, exhibits delay and power dissipation around 720ps and 840µW, respectively. These features reflect an overall improvement of 30% in the power-delay metric, when compared with the performance of other realizations recently published as well featured cells for low-power applications.

Study of Power-Delay Characteristics of a Mixed-Logic-Style Novel Adder Circuit at 90nm Gate Length

“…XOR-XOR based, XNOR-XNOR based, and XOR-XNOR based [1,2] depending upon the circuit approach to realize the two outputs: sum-S i, and carry-C i+1 . The mixed logic style architectures AL-1 and AL-2 reported in [6,7], and AL-3 proposed in this paper, together classified as another (4 th ) category, herein. The AL-1 and AL-2 architectures have been realized based on double pass logic (DPL) and CMOS transmission gate logic, resulting in mixed logic style implementation, whose block diagram and circuits are given in Fig.…”

“…The proposed adder architectures are based on the truth table shown in Table l; examining the truth table it can be observed that carry out (C i+1 ) is equal to (A i .B i ) value when carry in (C i ) equal to '0' and (A i +B i ) when carry in (C i ) is equal to '1'. Thus carry out (C i+1 ) can be generated by multiplexing Boolean functions (A i .B i ) and (A i +B i ) [6,7]. In addition to evaluating C i+1 in this approach, we propose the generation of sum (S i ) also by multiplexing A i .B i .C i and A i +B i +C i using C i+1 as the select signal, i.e., sum S i is equal to A i .B i .…”

“…The simulation of this circuit is done using Cadences' Spectre simulator. This architecture is referred herein as 'alternative logic-3' (AL-3) as an alternative to 1-bit adder circuits, recently reported in [6,7], called herein as 'alternative logic -1' (AL-1) and 'alternative logic-2' (AL-2), discussed in subsequent sections. We simulated and compared the performance metrics, such as worst case delay, and worst case power, and worst case PDP for AL-1, AL-2, and AL-3 circuits.…”

Implementation of Low Power CMOS Full Adders Using Pass Transistor Logic

“…Again, Ci can be used to select the respective value for the necessary condition, driving a multiplexer. Hence, an alternative logic scheme to design a full-adder cell can be formed by a logic block to obtain the A B and A B signals, another block to obtain the A.B and A+B signals, and two multiplexers being driven by the C input to generate the Sum and Co outputs, as shown in Figure 1 [13]. The characteristics and benefits of this logic structure are as follows.…”

“…As per the results obtained in [13], three new full-adders have been designed using the logic styles DPL and SR-CPL, and a new pass-transistor logic structure is presented in Fig. 4.…”