A Novel Low Power High Speed BEC for 2GHz Sampling Rate Flash ADC in 45nm Technology

Hussain, Sarfraz; Kumar, Rajesh; Trivedi, Gaurav

doi:10.1109/inis.2017.36

Cited by 5 publications

(2 citation statements)

References 10 publications

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“…The output of high velocity analogue to digital converters is essentially determined by the comparator. Lowpower and high-speed ADCs are critical building blocks in the front-end of a radio-frequency receiver in most modern telecommunication systems (Sarfraz Hussain, Kumar, and Trivedi 2017).…”

Section: Introductionmentioning

confidence: 99%

Construction of pMos Logic based Low Power High Speed Comparator Compare with nMos Logic

Reddy¹,

Dass²

2021

alinteri

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Aim: The aim of this work is to construct an innovative pMos logic based comparator and analyze the power consumption and compare with the nMos logic based comparator. Material and methods: The comparator is designed by using the Tanner tool version 16.01 for simulation and verification. By varying the length of a transistors in a circuit the power values were obtained. This experiment is performed for 20 different values of length. Results: The power consumption of a pMos logic based comparator was minimum (2.2656 ± 0.37933), followed by the nMos logic based comparator (7.7494 ± 0.41603), the less power consumption seen in pMos logic based comparator significance (.955). Conclusion: The consumption of power by the constructed pMos logic based comparator appears to have less power consumption than the nMos logic based comparator.

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Section: Introductionmentioning

confidence: 99%

Construction of pMos Logic based Low Power High Speed Comparator Compare with nMos Logic

Reddy¹,

Dass²

2021

alinteri

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“…In the first method, grey encoding is used [4], whereas, in the second method an OR gate [3] is employed. In the third method, an AND gate or any other possible circuit ([5, 6]) is utilised which converts thermometer code to one‐hot code. This paper presents three different types of bubble error correctors (BECs) which can be modified or redesigned for a specific binary encoder.…”

Section: Introductionmentioning

confidence: 99%

Methodology and comparative design of an efficient 4‐bit encoder with bubble error corrector for 1‐GSPS flash type ADC

Hussain

Kumar

Trivedi

2020

IET Circuits, Devices & Systems

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The design of a 4-bit encoder with a bubble error correction of first order is described in this study. Since encoder restricts speed of the flash analogue-to-digital converter (ADC), therefore, an improved and faster encoder is an essential requirement to push its limits. Encoder is divided into two parts: one-hot code generator [or bubble error corrector (BEC)] and binary encoder. Binary encoder proposed in this study is the modified Fat-Tree encoder of types I and II. Three types of BECs which have been compared in this study are OR gate based, NAND gate based and the proposed BEC. The proposed BEC consumes less power and provides better speed as compared to NAND based and OR gate based BECs. It can be further employed for higher order bubble correction as well. The proposed BEC consumes dynamic power of 87.071 μW and leakage power of 18.3563 pW exhibiting the delay of 38.3 ps with 1.8 V supply voltage and 1 GHz clock frequency. It has a power-delay product of 3.335 fJ, energy-delay product of 127.7305 Js and an intrinsic area of 4.753 mm 2 .

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ROM-Based Encoder with Bubble Error Correction

Bellavin

Budanov

2020

Springer Proceedings in Physics

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A Novel Low Power High Speed BEC for 2GHz Sampling Rate Flash ADC in 45nm Technology

Cited by 5 publications

References 10 publications

Construction of pMos Logic based Low Power High Speed Comparator Compare with nMos Logic

Construction of pMos Logic based Low Power High Speed Comparator Compare with nMos Logic

Methodology and comparative design of an efficient 4‐bit encoder with bubble error corrector for 1‐GSPS flash type ADC

ROM-Based Encoder with Bubble Error Correction

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