A novel low cost 65nm CMOS process architecture with self aligned isolation and W cladded source/drain

Blosse, A.; Ramkumar, K.; Gopalan, Padma; Hsu, Ching-Tien; Narayanan, Sundar; Narasimhan, G.; Gettle, R.; Kapre, R.; Sharifzadeh, Sahar

doi:10.1109/iedm.2004.1419256

Cited by 11 publications

(5 citation statements)

References 3 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…16. Interfacial resistance (Rc) between LRW and p+poly-Si is slightly higher than PVD-W, but its value is sufficiently low compared to spec-limit (3E-7 ohms-cm 2 ) [1,5], as shown in Fig. 17.…”

Section: A Physical Characterization Of W and Wn On Ti And Low Resismentioning

confidence: 94%

“…1) and abnormal high gate oxide leakage current of in pMOS at several sites [ Fig. 2], Ti/WN diffusion barrier is more suitable for the W-DPG application [1][2][3]. However, the tungsten film deposited on Ti/WN barrier shows not only more than twice higher electrical resistivity than WSix/WN barrier but also abnormally high gate sheet resistance (Rs) due to a narrow line width effect.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Low resistive tungsten dual polymetal gate process for high speed and high density memory devices

Kim

Lim

Sung

et al. 2007

ESSDERC 2007 - 37th European Solid State Device Research Conference

View full text Add to dashboard Cite

We developed ultra-low resistive tungsten dual polymetal gate memory device by using Ti-based diffusion barrier and a unique tungsten chemical vapor deposition (CVD) process with B 2 H 6 -based nucleation layer. The low resistive CVD-W (LRW) polymetal gate process not only reveals good gate oxide reliability comparable to PVD-W process, but also highly improved transistor performances such as signal delay characteristics.

show abstract

Section: A Physical Characterization Of W and Wn On Ti And Low Resismentioning

confidence: 94%

Section: Introductionmentioning

confidence: 99%

Low resistive tungsten dual polymetal gate process for high speed and high density memory devices

Kim

Lim

Sung

et al. 2007

ESSDERC 2007 - 37th European Solid State Device Research Conference

View full text Add to dashboard Cite

show abstract

“…9) Also, an amorphous-phase deposited WSi x layer could act as a low-resistivity diffusion barrier because the diffusivities in amorphous materials are several orders of magnitude lower than those of corresponding polycrystalline materials. 10) Recently, in the gate electrode process, thermally stable WSi x /WN and Ti/(TiN)/WN barriers [11][12][13][14][15][16] were proposed for the reduction of gate R c between tungsten and poly-Si. In the case of the WSi x /WN barrier, 11) W-Si-N formed by the reaction between nitrogen dissociated from WN and amorphous WSi x could lead to a partial reduction of Si-N dielectric formation, which could effectively reduce gate R c .…”

Section: Introductionmentioning

confidence: 99%

Dependence of Gate Interfacial Resistance on the Formation of Insulative Boron–Nitride for p-Channel Metal–Oxide–Semiconductor Field-Effect Transistor in Tungsten Dual Polygate Memory Devices

Sung¹,

Lim²,

Cho³

et al. 2008

jjap

View full text Add to dashboard Cite

We investigated the effect of boron at the interface of the diffusion barrier in tungsten polymetal gate stacks on the gate contact interfacial resistance between tungsten and p+ polycrystalline silicon (poly-Si). B-N formation can occur at the bottom of WN, which is a crucial layer for preventing abnormal tungsten silicidation between the tungsten gate electrode and poly-Si. Dissociated nitrogen from the WN layer during postdeposition thermal treatment could easily interact with outdiffused boron, creating an insulating B-N compound layer that could lead a significant increase in gate contact resistance. We varied the types of diffusion barriers (WSi x , Ti, TiN, and WN inserted) to investigate the effect of the B-N interlayer on gate contact resistance. The boron concentration at the region of B-N formation is consistent with not only electrically measured gate contact resistance and but also ring oscillator delay characteristics. In the case of the Ti/WN barrier, the TiB 2 compound layer existing inside TiSi 2 created by the reaction between Ti and p+ poly-Si could behave as efficient buffer layers preventing the out-diffusion of boron during annealing. TiN deposited on the poly-Si induces Si-N interdielectric formation, which also increases gate contact resistance. For the WSix/WN barrier case, additional deposition of an amorphous-Si layer could suppress boron diffusion, but is less effective than the Ti/WN barrier.

show abstract

“…Recently, some reports have been made on the application of Ti insertion into a W polygate stack with a low-gate R c value. 6,7) However, detailed analysis of interfacial characteristics for the TiSi x / TiN diffusion barrier has not been carried out.…”

Section: Introductionmentioning

confidence: 99%

Roles of Ti, TiN, and WN as an Interdiffusion Barrier for Tungsten Dual Polygate Stack in Memory Devices

Sung¹,

Lim²,

Cho³

et al. 2007

jjap

View full text Add to dashboard Cite

Tungsten dual polygate (W-DPG) stacks with diffusion barriers formed by the Ti(N) process were investigated in terms of gate contact resistance (R c ) and the polydepletion effect. The Ti layer in the Ti/WN diffusion barrier is found to be converted into a TiSi x /TiN bilayer during the postdeposition annealing process. The TiSi x reaction between Ti and p+ polycrystalline silicon (poly-Si) effectively prevents the formation of a parasitic dielectric layer, which could lead to low-gate R c . The TiN reaction between Ti and WN minimizes the occurrence of the TiSi x reaction, which effectively reduces p+ polydepletion caused by the out-diffusion of boron during the postdeposition annealing process. Therefore, poly-Si/Ti/WN/W could be a promising tungsten dual polygate stack, which satisfies high-speed requirements in dynamic random-access memory (DRAM) devices.

show abstract

A novel low cost 65nm CMOS process architecture with self aligned isolation and W cladded source/drain

Cited by 11 publications

References 3 publications

Low resistive tungsten dual polymetal gate process for high speed and high density memory devices

Low resistive tungsten dual polymetal gate process for high speed and high density memory devices

Dependence of Gate Interfacial Resistance on the Formation of Insulative Boron–Nitride for p-Channel Metal–Oxide–Semiconductor Field-Effect Transistor in Tungsten Dual Polygate Memory Devices

Roles of Ti, TiN, and WN as an Interdiffusion Barrier for Tungsten Dual Polygate Stack in Memory Devices

Contact Info

Product

Resources

About