A novel logic compatible gain cell with two transistors and one capacitor

Abstract

In consumer electronics, cost-effective embedded memory technology is an important subject. We propose a novel, cost-effective gain cell for memory embedded in logic LSIs. The new cell consists of two conventional bulk transistors and one MOS capacitor. It can be fabricated using the pure logic process with a few additional process steps. The fabrication cost of this cell is lower than that of DRAM or SRAM at a memory density in the 1-100Mbit range.

Review and classification of gain cell eDRAM implementations

“…Several authors are not very specific about their target applications [7,10,24], as they only mention general SoCs. However, they follow the same trend as the aforementioned processor community by proposing GC memories as a replacement for the mainstream 6T SRAM solution.…”

“…However, the conventional 1-transistor, 1-capacitor (1T-1C) eDRAM requires costly process adders, and provides limited voltage downscaling, while requiring frequent power consuming refresh operations [6][7][8]. A partial solution to these drawbacks is provided by logic compatible gain-cell (GC) eDRAMs [7]. While the concept of gain cells dates back to the early 1970's, they fell into oblivion due to the predominant development of dedicated process technologies for stand-alone SRAM and DRAM chips.…”

Design and failure analysis of logic-compatible multilevel gain-cell-based dram for fault-tolerant VLSI systems

“…We shall first compare the GCs of previously proposed logic-compatible single-bit-per-cell macro memories [4,9,[11][12][13]16] to find the GC topology that is best suited for multilevel operation. Subsequently, different transistor configurations are discussed to optimize the area of the storage array while maintaining good reliability.…”

“…The 2T1MOSCAP gain cell requires a large MOS capacitor and also two additional process steps to implement very high threshold voltage transistors [9]. The 2-transistor-1-diode (2T1D) GC [12] uses the ST also as read transistor (RT), thereby saving silicon area.…”

“…They can be smaller than the SRAM 1-bit storage cell and, as opposed to conventional 1T1C eDRAMs, they can be fully compatible with standard digital CMOS technologies and they allow for a non-destructive read operation. Various GC-based DRAMs with different basic cell structures have been proposed during the last decade [4,9,12,13,16]. However, to the best of our knowledge, the possibility of storing multiple levels (more than one bit) per GC has not been exploited yet.…”