A novel high-speed latching operation flip-flop (HLO-FF) circuit and its application to a 19-Gb/s decision circuit using a 0.2-μm GaAs MESFET

Murata, Koichi; Otsuji, T.; Sano, Eiichi; Ohhata, M.; Togashi, M.; Suzuki, Masao

doi:10.1109/4.466072

Cited by 40 publications

(7 citation statements)

References 6 publications

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“…By increasing the track pair current relative to the latch current, the track dynamic characteristics such as setup time and propagation delay can be improved while preserving the basic static nature of the latching circuit. This is similar to the "HLO-FF" approach in (10), which separates the track and latch pair currents, resulting in up to 30% improvement in switching speeds, but with some increase in the minimum operating clock frequency of the flip-flop if the ratio is made too high. Our approach differs from the "HLO-FF" approach in that a single current source is shared between master and slave, which considerably simplifies the layout, and an emitter degeneration resistor is used instead of scaling device geometries, which allows us to finely adjust the ratio of currents and use minimum device geometries throughout the design.…”

Section: Divider Circuit Design and Performancementioning

confidence: 83%

CANTILEVERED BASE InP DHBT FOR HIGH SPEED DIGITAL APPLICATIONS

Gutierrez-Aitken

Kaneshiro

Matsui

et al. 2001

Int. J. Hi. Spe. Ele. Syst.

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High speed digital logic is essential in diverse applications such as optical communication, frequency synthesizers, and analog-digital conversion. Current research efforts indicate that technologies utilizing heterojunction bipolar transistors (HBT) are the preferred approach for systems operating at clock frequencies of 40 GHz and above (1-6). In this paper we report a novel InAlAs/InGaAs/InP double-HBT (DHBT) with a cantilevered base layer and undercut collector. We fabricated and demonstrated an 80 GHz 2:1 digital frequency divider, and a 5 GHz 8-bit phase/7-bit magnitude Direct Digital Synthesizer (DDS) chip with approximately 3000 transistors using this technology.

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Section: Divider Circuit Design and Performancementioning

confidence: 83%

CANTILEVERED BASE InP DHBT FOR HIGH SPEED DIGITAL APPLICATIONS

Gutierrez-Aitken

Kaneshiro

Matsui

et al. 2001

Int. J. Hi. Spe. Ele. Syst.

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“…However, the fundamental physics properties of the devices, f T and f max , usually limit the maximum operating frequency of a static divider. Thus, intensive efforts are under way to improve the circuit structures and overcome the inherent limitations of device, such as HLO-FF [3,4] and superdynamic structure [5][6][7][8][9].…”

Section: Introductionmentioning

confidence: 99%

11.8 GHz GAINP/GAAS HBT dynamic frequency divider using HLO‐FF technique

Wei

Meng

Chang

et al. 2008

Micro & Optical Tech Letters

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determined by the 3-dB AR, is about 540 MHz or 20.8% (2.33-2.87 GHz) and 480 MHz or 19.6% (2.21-2.69 GHz) with minimum AR of 0.87 dB at 2.6 GHz and 0.88 dB at 2.45 GHz, respectively, for L t ϭ 0 and L t ϭ 19 mm. Both of the CP bandwidths are larger than 19%. It is evident that the length of the protruded metallic strips has larger effect on the port isolation level, but has less effect on the CP bandwidth. As for the antenna with L t ϭ 19 mm, both impedance matching (referred to 10 dB return loss) and low coupling level (referred to 20 dB isolation) are achieved within the CP operating band. Figure 4 shows the measured far-field radiation patterns of the antenna with length of L t ϭ 19 mm at 2.45 GHz in the LHCP and RHCP operation. It is observed that the cross-polarization levels are about 26 dB in the broadside direction in both states. The maximum radiation direction of the antenna displaces a little from the z-axis. It should be noted that the backside radiation pattern is a mirror image of the front pattern, and the polarization senses of both sides are opposite to each other. The antenna radiates almost the same amount of energy into both sides. CONCLUSIONA novel design of broadband dual CP square slot antenna has been investigated and successfully implemented. Two orthogonal modes of the proposed antenna are excited in series through the coupling between the T-junction and the T-shaped strip. By loading the four metallic strips at the slot corners, high port isolation level is achieved. The measured 3-dB AR bandwidth is 480 MHz or 19.6% and the isolation between two ports is better than 20 dB over the band. The proposed antenna has excellent dual CP characteristics and is suitable for polarization diversity operation.

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“…Introduction: As demands increase on higher data-rate communication systems, the speed of a D-type flip-flop plays an important role in most digital circuits. Use of circuit topology to compensate for the inherent limitations of the device was reported in [1][2][3]. The superdynamic D-type flip-flop with an ECNFP has the fastest speed.…”

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confidence: 99%

“…Emitter couple logic (ECL) topology is employed to achieve the properties of high speed and low input sensitivity. Based on the concept of the HLO-FF (high-speed latching operation flip-flop) structure [1], ECNFPs are inserted in the regenerative pairs by the cascode manner to limit logic voltage swing to R L (I read À I latch )=2 and increase the maximum operating frequency. The logic information is stored only during the clock switching time, and then decays during the equilibrium state [2,3].…”

mentioning

confidence: 99%