A Novel High Speed FPGA Architecture for FIR Filter Design

Low power residue number system using lookup table decomposition and finite state machine based post computation

“…The maximum frequency of the filter for the 8-bit word length is 57.3MHz, while the maximum frequency of the filter for the 12-bit and 16-bit word lengths is limited by the accumulation of reverse conversion results. The state-of-the-art comparison of proposed FIR design with other FPGA RNS FIR methods for three moduli set with a 32-bit unsigned input for a Xilinx Spartan 3E FPGA device has reduced 50% power dissipation and the frequency component is increased by 36.56% in proposed FSM decomposed RNS FIR design [30], [31]. Observation from Figure 3 can be made that the performance trade-off comparison for the conventional reverse computation of RNS with the proposed model, the filter tap extension with the logical elements were compared and the total performance loss is smaller when tested with possible higher-order during FIR filter design.…”

“…The suggested RNS system takes advantage of inherent concurrency within residue channels as well as FPGA device capabilities. In Table 1, the 8 bit word length for moduli set (7,8,9) the area is decreased by 4.5% whereas for 16 bit word length for moduli set (31,32,33) the area is decreased by 15.36%. In 8 bit word length for moduli set (7,8,9) the frequency component is increased by 24.08% whereas for 16 bit word length for moduli set (31,32,33) the frequency is improved by 16.18%.…”

“…In Table 1, the 8 bit word length for moduli set (7,8,9) the area is decreased by 4.5% whereas for 16 bit word length for moduli set (31,32,33) the area is decreased by 15.36%. In 8 bit word length for moduli set (7,8,9) the frequency component is increased by 24.08% whereas for 16 bit word length for moduli set (31,32,33) the frequency is improved by 16.18%. In Table 2, the 4 tap FIR filter, area in the proposed method is decreased by 4.15% and the frequency component is increased by 13.30% whereas in 16 tap FIR filter area is decreased by 4.98% and the frequency is increased by 19.57% when compared with the conventional reverse computation method.…”

FPGA Implementation of Higher Order FIR Filter

“…Meher et al [6] reported the design optimization of one and two dimensional fully pipelined computing structures for area delay-power-efficient implementation of FIR filter by using the systolic decomposition of distributed arithmetic based inner product computation. The main components of digital FIR filters design on FPGAs are the register bank to save the samples of signals, adder to implement sum operations and multiplier for multiplication of filter coefficients to signal [7]. Although, design and implementation of digital FIR filters seem simple but the design bottleneck is multiplier block for speed, power consumption and FPGA chip area occupation.…”