A Novel High-Efficiency Gate Drive Circuit for Normally Off-Type GaN FET

Umegami, Hirokatsu; Hattori, Fumiya; Nozaki, Yu; Yamamoto, Masaaki; Machida, Osamu

doi:10.1109/tia.2013.2267512

Cited by 26 publications

(8 citation statements)

References 8 publications

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“…This is because the energy stored in the loop inductance and the dv/dt stress increase with the current [5], [17]. Although V SD is known to increase in accordance with V GS OF F [14]- [16] and consequently dead time losses are expected to increase, this work demonstrates that the application of a negative gate voltage V GS OF F in GaN FETs is more complex. First, the large V SD caused by the negative gate voltage V GS OF F requires extremely short dead-times to provide a good efficiency and keep the bootstrap voltage within the allowed limits.…”

Section: State Of Current Research and Aim Of This Workmentioning

confidence: 90%

“…Nevertheless, in synchronous DC-DC buck converters using enhancement mode GaN FETs, the focus has been on gate drives which keep the device turned off by applying zero volt to V GS . Although loss measurements have been carried out for an inverter circuit with a negative gate voltage V GS OF F [15], and a novel gate drive circuit for an LLC converter has been proposed [16], the topic of GaN enhancement FETs in hard switched DC-DC buck converter using negative gate voltages has mainly been ignored in the literature. For high current and high frequency converter, the threshold voltage with V GS at 0 V may be too low.…”

Section: State Of Current Research and Aim Of This Workmentioning

confidence: 99%

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Investigation of dead-time behaviour in GaN DC-DC buck converter with a negative gate voltage

Roschatt

McMahon

Pickering

2015

2015 9th International Conference on Power Electronics and ECCE Asia (ICPE-ECCE Asia)

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The low threshold voltage of Gallium Nitride enhancement mode FETs is a concern in high current high frequency synchronous DC-DC buck converters. Applying a negative gate voltage to the low side FET to improve the dV/dt robustness increases the voltage drop between source and drain during dead-time conduction. This has consequences not only on the efficiency, but more importantly on the bootstrap voltage. Even with precise dead-timing, the large voltage drop from drain to source still results in a significant variation of the bootstrap voltage. This results in a change of gate turn on speed and increases the dV/dt stress. The very short dead-time needed to avoid great variations in the bootstrap voltage means that the voltage drop from source to drain can no longer bet treated as a constant as it varies greatly during the dead-time.

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Section: State Of Current Research and Aim Of This Workmentioning

confidence: 90%

Section: State Of Current Research and Aim Of This Workmentioning

confidence: 99%

Investigation of dead-time behaviour in GaN DC-DC buck converter with a negative gate voltage

Roschatt

McMahon

Pickering

2015

2015 9th International Conference on Power Electronics and ECCE Asia (ICPE-ECCE Asia)

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“…Sanken has developed devices using a non-insulated recessed gate as shown in Fig. 8 (d) [44], [47]. However, Sanken has not published whether this technique is used in the device it is currently sampling.…”

Section: Enhancement-mode Devicesmentioning

confidence: 99%

Review of Commercial GaN Power Devices and GaN-Based Converter Design Challenges

Jones

Wang

Costinett

2016

IEEE J. Emerg. Sel. Topics Power Electron.

878

324

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GaN power devices are an emerging technology that have only recently become available commercially. This new technology enables the design of converters at higher frequencies and efficiencies than those achievable with conventional Si devices. This paper reviews the characteristics and commercial status of both vertical and lateral GaN power devices, providing the background necessary to understand the significance of these recent developments. Additionally, the challenges encountered in GaN-based converter design are considered, such as the consequences of faster switching on gate driver design and board layout. Other issues include the unique reverse conduction behavior, dynamic Rds,on, breakdown mechanisms, thermal design, device availability, and reliability qualification. This review will help prepare the reader to effectively design GaN-based converters as these devices become increasingly available on a commercial scale.

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“…Because the fabricated D-mode GaN FET did not contain a body diode between the source and drain, the reverse I-V characteristics in the third quadrant are represented by the triangles in Figure 4. According to [27], the reverse drain-source voltage increased with the magnitude of the negative gate-source voltage, resulting in power loss. An additional SiC SBD with an antiparallel connection to the fabricated cascode GaN FET can not only reduce the reverse recovery time [16] but also limit the forward drop voltage under the turn-off condition (represented by the circles in Figure 4).…”

Section: Mis-hemt and LV Mosfet Transfer Curve Characteristicsmentioning

confidence: 99%

Simulation Model Development for Packaged Cascode Gallium Nitride Field-Effect Transistors

Jeng

2017

Crystals

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This paper presents a simple behavioral model with experimentally extracted parameters for packaged cascode gallium nitride (GaN) field-effect transistors (FETs). This study combined a level-1 metal-oxide-semiconductor field-effect transistor (MOSFET), a junction field-effect transistor (JFET), and a diode model to simulate a cascode GaN FET, in which a JFET was used to simulate a metal-insulator-semiconductor high-electron-mobility transistor (MIS-HEMT). Using the JFET to simulate the MIS-HEMT not only ensures that the curve fits an S-shape transfer characteristic but also enables the pinch-off voltages extracted from the threshold voltage of the MIS-HEMT to be used as a watershed to distinguish where the drop in parasitic capacitance occurs. Parameter extraction was based on static and dynamic characteristics, which involved simulating the behavior of the created GaN FET model and comparing the extracted parameters with experimental measurements to demonstrate the accuracy of the simulation program with an integrated circuit emphasis (SPICE) model. Cascode capacitance was analyzed and verified through experimental measurements and SPICE simulations. The analysis revealed that the capacitance of low-voltage MOSFETs plays a critical role in increasing the overall capacitance of cascode GaN FETs. The turn-off resistance mechanism effectively described the leakage current, and a double-pulse tester was used to evaluate the switching performance of the fabricated cascode GaN FET. LTspice simulation software was adopted to compare the experimental switching results. Overall, the simulation results were strongly in agreement with the experimental results.

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A Novel High-Efficiency Gate Drive Circuit for Normally Off-Type GaN FET

Cited by 26 publications

References 8 publications

Investigation of dead-time behaviour in GaN DC-DC buck converter with a negative gate voltage

Investigation of dead-time behaviour in GaN DC-DC buck converter with a negative gate voltage

Review of Commercial GaN Power Devices and GaN-Based Converter Design Challenges

Simulation Model Development for Packaged Cascode Gallium Nitride Field-Effect Transistors

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