A novel FSK demodulation method using short-time DFT analysis for LEO satellite communication systems

IEEE J. Solid-State Circuits

2007

Abstract-This paper deals with the system and circuit-level aspects of an ultra-low-power robust wireless node for an asymmetric wireless link. A single building block TX front-end for a frequency hopping spread spectrum (FHSS) transmitter implemented in silicon-on-anything (SOA) bipolar technology is presented. It is realized with a directly modulated RF cascoded Colpitts power voltage-controlled oscillator (VCO), a frequency locked loop for center frequency calibration, and a digital pre-distortion algorithm for accurate frequency bins synthesis. The TX front-end draws only 1 mA at 18 dBm output power. By combining digital system techniques for frequency hopping and merging the VCO and the power amplifier (PA), a robust solution is obtained for indoor ultra-low-power wireless links. The proposed pre-distortion concept allows reduction of the hardware complexity, while the combination of a cascode output buffer and a common-collector Colpitts VCO allows us to reduce the complete FHSS front-end to a single building block that directly drives the antenna through a balun. A dedicated digital algorithm on the receiver side reduces the center frequency offset from a maximum value of 8.2 MHz to less than 8 ppm avoiding the use of any crystal on the transmitter side. Precision in the hopping synthesis is obtained by employing a ST-DFT based demodulator with differential encoding and an offset sending technique. The novel FHSS-predistortion concept has been verified by realizing a full wireless link that achieves a bit error rate better than 1.1% at 25 dBm output power while transmitting across an 8 meters indoor non-line-of-sight (NLOS) path.

Section: Simulation and Experimental Resultsmentioning

confidence: 99%

“…As shown in [8], the capability of the ST-DFT algorithm to reject the frequency offset depends upon the condition that the offset is slowly varying. In other words, the frequency offset should vary at a rate smaller than the data rate.…”

Section: B Data Recoverymentioning

confidence: 99%

A 1 mA Ultra-Low-Power FHSS TX Front-End Utilizing Direct Modulation With Digital Pre-Distortion

IEEE J. Solid-State Circuits

2007

“…This demodulator is based on the Short-time DFT algorithm and has been proposed for low earth orbit (LEO) satellite communication systems [4]. A block diagram of a ST-DFT receiver is depicted in Fig.4.…”

Section: Short-time Dft Demodulatormentioning

confidence: 99%

“…• Arctan-differentiated demodulator (ADM) [1] • Correlation demodulator [2] • Digital cross-differentiate multiply demodulator (DCDM) [3] • Short-time DFT (ST-DFT) demodulator [4] Another widely used digital demodulator is the zero-crossing demodulator. Unfortunately in [5] it has been shown that when the frequency offset is equal to the 6% of the data rate, the SNR degradation reaches 4.8 dB.…”

Section: Bfsk Demodulationmentioning

confidence: 99%

A FSK demodulator comparison for ultra-low power, low data-rate wireless links in ISM bands

Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005.

Personal communications require wireless nodes, which can transmit and receive reliably data under huge power constraints. Higher level of integration and reduction of power consumption can be achieved using a zero-IF architecture together with a wideband BFSK modulation scheme. Unfortunately FSK techniques performances degrade sharply in the presence of frequency offset. In this paper a comparison between potentially low power BFSK architectures is presented based on high level models. In depth analysis of four potentially low power demodulators shows that the architecture, which can assure rejection of large static offset with minimum increment in hardware complexity is the ST-DFT based demodulator. This will allow great reduction in power consumption avoiding acquisition and tracking of the offset at the receiver side.

“…The DAC will convert these digital codes into an analog voltage, which drives the fine-tune varactors of the VCO. The required accuracy in the frequency synthesis is obtained by employing digital pre-distortion together with a frequency offset insensitive demodulator [4]. The coarse tuning range should be large enough to cope with the capacitances and inductance spread while the fine tuning range should be large enough to synthesize at least 50 hopping channels as required by the FCC rules.…”

Section: System Architecturementioning

confidence: 99%

A Sub-mA FH Frequency Synthesizer Technique

IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2006

A novel frequency-hopping spread-spectrum transmitter architecture is presented that provides robust communications in the 915 MHz ISM band while dissipating very low power. The frequency-hopping front-end consists of a VCO, dividers and output stage. A base-band predistortion algorithm allows hopping with minimum hardware complexity. The TX front-end has been fabricated in Silicon-on-Anything (SOA) bipolar technology and a BFSK modulated wireless link using a dedicated receiver has been realized. A 1kbps, 1khop/s link with a BER smaller than 1.1 % has been achieved at -25 dBm output power while having 64 orthogonal channels. The synthesizer architecture (VCO+divider+base-band) dissipates only 870µA.