A novel framework for exploring 3-D FPGAs with heterogeneous interconnect fabric

Abstract

A heterogeneous interconnect architecture can be a useful approach for the design of 3-D FPGAs. A methodology to investigate heterogeneous interconnection schemes for 3-D FPGAs under different 3-D fabrication technologies is proposed. Application of the proposed methodology on benchmark circuits demonstrates an improvement in delay, power consumption, and total wire-length of approximately 41%, 32%, and 36%, respectively, as compared to 2-D FPGAs. These improvements are additional to reducing the number of interlayer connections. The fewer interlayer connections are traded off for a higher yield. An area model to evaluate this trade-off is presented. Results indicate that a heterogeneous 3-D FPGA requires 37% less area as compared to a homogeneous 3-D FPGA. Consequently, the heterogeneous FPGAs can exhibit a higher manufacturing yield. A design toolset is also developed to support the design and exploration of various performance metrics for the proposed 3-D FPGAs.

Three Dimensional FPGA Architecture with Fewer TSVs

“…Since the area of a TSV is much larger than that of a horizontal metal wire, such architectures are still infeasible because of the area overhead. To reduce the number of interlayer connections, Siozios et al designed a 3D FPGA that combines 2D and 3D SBs [3]. This approach achieved remarkable area, delay, and power improvements Copyright c 2018 The Institute of Electronics, Information and Communication Engineers when compared with a 3D FPGA based entirely on 3D SBs, but designing an FPGA in which the tiles have large differences in structure and size is not easy.…”

Power Efficient Data-Aware SRAM Cell for SRAM-Based FPGA Architecture

“…Power consumption in interconnect dominates dynamic power in FPGAs [62][63][64] due to the interconnect structure, which consist of prefabricated wire segments. Each segment is attached with used and unused switches.…”

Three-Dimensional Tree-Based FPGA: Architecture Exploration Tools and Technologies

“…We have seen numerous studies [1,2,5,7,8] shows that the switch blocks (SBs) is the most area-consuming unit compared to other design elements in 2D Meshbased FPGAs and this situation is becoming even worse in 3D Mesh-based FPGAs because the TSVs are located on 3D-SBs. Although the design and manufacturing engineers are trying to reduce TSV dimensions, the minimum feature size on the die is also shrinking.…”

“…The average improvement in speed measured for horizontally partitioned stacking methodology is 65.13 and 43.52 % for vertical partitioning method. The horizontally partitioned 3D stack methodology performed 1.7 times faster compared to 3D Mesh-based Industrial FPGA with identical logic resources [5]. The 3D Mesh-based FPGA reported in [5] with intermittent 2D and 3D switch blocks distribution estimated an average speed improvement of 38.3 % for identical logic density and array size.…”

“…Moreover it has been reported in [1,2,4] that the TSV utilization is actually quite low if the 3D-SBs are with full vertical connectivity in use. Many other recent research results also point out that the utilization of TSVs is actually very low in 3D Mesh-based FPGAs [2,4,5] with full vertical connectivity, which motivated us to explore Tree-based interconnect network, that can be optimized to achieve higher speed, reduced power consumption, area and increased logic density. As described in Chaps.…”